library ieee;
use ieee.std_logic_1164.all;

entity dff9 is
  port (  din:  in std_logic_vector(8 downto 0);
	  clk:  in std_logic;
      dout: out std_logic_vector(8 downto 0)
       );
 end dff9;

 architecture a of dff9 is
 begin

	main:process(clk)
	begin
      if (clk'event and clk='1') then  
	  -- rising edge of clock
	  dout <= din;
          end if;
        end process main;
 end a;


<div align="center"><br /><script type="text/javascript"><!--
google_ad_client = "pub-7293844627074885";
//468x60, Created at 07. 11. 25
google_ad_slot = "8619794253";
google_ad_width = 468;
google_ad_height = 60;
//--></script>
<script type="text/javascript" src="http://pagead2.googlesyndication.com/pagead/show_ads.js">
</script><br />&nbsp;</div>