-- 
-- Program 
-- C:\CAO\EXEMPLAR\BIN\PC\FPGA.EXE C:\TEMP\ORIGINAL\REG1.VHD C:\TEMP\RTL\REG1.V
-- HD -COMMAND_FILE=C:\CAO\EXEMPLAR\BIN\PC\TMP20.$$$ 
-- Version V2.1.7
-- Definition of  REG1
-- 
-- VHDL Concurrent Statements, created by
-- Exemplar Logic's CORE
--      Fri Nov 17 13:01:27 1995
-- 
-- 
-- 

library exemplar ;
use exemplar.exemplar_1164.all ;
library ieee ;
use ieee.std_logic_1164.all ;

entity REG1 is
   port (
      D, C : in std_logic ;
      Z : inout std_logic) ;
end REG1 ;

architecture exemplar of REG1 is
   signal
      vh_1, vh_2: std_logic ;
 
begin
   Z <= (vh_2) or (vh_1) ;
   vh_1 <= (C and D) ;
   vh_2 <= (Z and  not C) ;

end exemplar ;

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