-- -- Program -- C:\CAO\EXEMPLAR\BIN\PC\FPGA.EXE C:\TEMP\ORIGINAL\REG3.VHD C:\TEMP\RTL\REG3.V -- HD -COMMAND_FILE=C:\CAO\EXEMPLAR\BIN\PC\TMP22.$$$ -- Version V2.1.7 -- Definition of REG3 -- -- VHDL Concurrent Statements, created by -- Exemplar Logic's CORE -- Fri Nov 17 13:02:13 1995 -- -- -- library exemplar ; use exemplar.exemplar_1164.all ; library ieee ; use ieee.std_logic_1164.all ; entity REG3 is port ( D, C, A : in std_logic ; Z : out std_logic) ; end REG3 ; architecture exemplar of REG3 is signal FLAGr1, vh_0, vh_1, vh_2: std_logic ; begin vh_0 <= (A and D) ; vh_1 <= '0' ; vh_2 <= '0' ; Z <= (FLAGr1 and vh_0) ; DFFPC( D, vh_1, vh_2, C, FLAGr1) ; end exemplar ; <div align="center"><br /><script type="text/javascript"><!-- google_ad_client = "pub-7293844627074885"; //468x60, Created at 07. 11. 25 google_ad_slot = "8619794253"; google_ad_width = 468; google_ad_height = 60; //--></script> <script type="text/javascript" src="http://pagead2.googlesyndication.com/pagead/show_ads.js"> </script><br /> </div>