--------  VHDL Repository Prolog ------------
--
-- Unit name    :
-- Version      :
-- Author       :
--              :
-- DDN Address  :
-- Copyright    : (c)
-- Date created :
-- Release date :
-- Last update  :
-- VHDL Version :
-- Machine/System Analyzed/Simulated on:
---------------------------------------------------------------
-- Keywords     :
-- Abstract     :
------------------ Revision history ---------------------------
-- DATE         VERSION AUTHOR       HISTORY
--
------------------ Distribution and Copyright -----------------
-- This prologue must be included in all copies of this VHDL code.
--
-- This description is copyright by the author.
--
-- This description is released to the VHDL community.

-- Restrictions on use or distribution:  NONE
------------------ Disclaimer ---------------------------------
-- This VHDL description code and its documentation are provided
-- "AS IS" and without any expressed or implied warranties
-- whatsoever.  No warranties as to performance, merchantability,
-- or fitness for a particular purpose exist.
--
-- Because of the diversity of conditions under which this code
-- may be used, no warranty of fitness for a particular purpose
-- is offered.  The user is advised to evaluate the code
-- thoroughly before relying on it.  The user must assume the
-- entire risk and liability of using this code.
--
-- In no event shall any person or organization of people be
-- held responsible for any direct, indirect, consequential
-- or inconsequential damages or lost profits.
-------------------END-PROLOG--------------------------------


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