LFSR Counter Sample Project

This page allows you to look at what goes into a simple FPGA project. The target architecture is a GERM prototype module, which can be programmed using the xchecker cable from a PC and tested using the HP logic analyzers in room 02G.

Click here to browse the contents of the project directory.

Four bit LFSR Counter

Inputs:: Clock: input to all FPGA flip-flops; CE: count enable; CLR: synchronous clear to all zeros
Outputs:: Count: 4-bit LFSR counter (has cycle length 15)

A linear feedback shift register is a counter that is very fast and requires very few resources. It counts in a pseudorandom sequence that that repeats after 2^N-1 cycles. At each step, the bits simply shift left one bit, and into the low bit is shifted some XOR or XNOR combination of the previous bits. For a four bit 15 cycle LFSR, the feedback bit is the XNOR of the two most significant bits. The pattern of all ones in the only pattern skipped in the 15-cycle.

Testing the GERM design

Once the design is successfully synthesized and run through XMAKE, the BIT file must be downloaded to the FPGA. Put the Yugo GERM board into the gray box for power and clock signals. Turn on the gray box and the HP logic analyzer. Connect the "xchecker" cable from the PC printer port to the GERM board. After using ftp to get the BIT file onto the PC, run "xchecker" and enter the name of your BIT file.

The LFSR project uses two switch inputs, CLR and CE, connected to switches 4 and 5. After determining which switches are which, verify that the 4 bit output waveforms are correct on the logic analyzer.

Created by Scott E. Harrington, Duke Electrical Engineering