library IEEE;
use  IEEE.STD_LOGIC_1164.all;
use  IEEE.STD_LOGIC_ARITH.all;
use  IEEE.STD_LOGIC_UNSIGNED.all;

entity test_bad is

  port (
     state :  in  std_logic_vector(3 downto 0);
     cin :   in std_logic;

     cout_a: out  std_logic;
     cout_b: out  std_logic
  );

end test_bad;

architecture a of test_bad is

 begin

   main:process (state,cin)
    begin

      cout_a <= '0';
      cout_b <= '0';
      -- This should be combinational logic since there are
      -- default assignments for every output. However, under
      -- Student Version 7.21, this generates a latch for both
      -- cout_a, cout_b outputs.  Under the latest profession version
      -- this is fixed.  The solution is to add a 'else' clause for every
      -- conditional output assignment.

       if (state = "0010") then
	   if (cin = '1') then
            cout_a <= '1';
           end if;
       end if;
       
       if (state = "0011") then
	     cout_b <= '1';
       end if;

     end process main;

end a;

	     


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