-------------------------------------------------------------------------------
--
-- Project : ATEP
-- File name : uartxmt.vhd
-- Title : UART XMT
-- Description : UART Transmit selection
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Author Revision Comments
-- Sat Oct 29 10:05:49 1994 cohen Rev A Creation
-------------------------------------------------------------------------------
entity UartXmt_Nty is
port (Shift_LdF : in bit;
ClkEnbT : in bit;
Clk : in bit;
DataT : in Bit_Vector(7 downto 0);
ResetF : in bit;
Serial_OuT : out bit;
XmitMT : out boolean);
end UartXmt_Nty;
architecture UartXmt_Beh of UartXmt_Nty is
subtype Int0to9_Typ is integer range 0 to 9;
signal XmitReg_s : Bit_Vector(9 downto 0); -- the transmit register
signal Count_s : Int0to9_Typ; -- # of serial bits sent
begin -- UartXmt_Beh
-----------------------------------------------------------------------------
-- Process: Xmit_Lbl
-- Purpose: Models the transmit register of a UART.
-- Operation is as follows:
-- . All operations occur on rising edge of CLK.
-- . If ResetF = '0' then
-- XmitReg_s is reset to "1111111111".
-- Count_s is reset to 0.
-- . If ClkEnbT = '1' and Shift_LdF = '0' and ResetF = '1' then
-- '1' & DataT & '0' get loaded into XmitReg_s.
-- Count_s is reset to 0
-- . If ClkEnbT = '1' and Shift_LdF = '1' and ResetF = '1' then
-- '1' & XmitReg_s(9 downto 1) get loaded into XmitReg_s
-- (shift right with a '1' shifted in)
-- Count_s is incremented to no more then 10
-- (i.e. if it is 9, then it stays at 9)
--
-----------------------------------------------------------------------------
Xmit_Lbl : process
variable Count_v : natural;
begin -- process Xmit_Lbl
wait until Clk'event and Clk = '1'; -- rising edge of clock
if ResetF = '0' then
XmitReg_s <= "1111111111";
Count_s <= 9;
elsif ClkEnbT = '1' and Shift_LdF = '0' and ResetF = '1' then
XmitReg_s <= '1' & DataT & '0';
Count_s <= 0;
elsif ClkEnbT = '1' and Shift_LdF = '1' and ResetF = '1' then
XmitReg_s <= '1' & XmitReg_s(9 downto 1);
if Count_s /= 9 then
Count_s <= Count_s + 1;
end if;
end if;
end process Xmit_Lbl;
-------------------------------------------------------------------------------
-- Concurrent signal assignment for Serial_Out
-- where Serial_Out is equal to XmitReg_s(0)
-------------------------------------------------------------------------------
Serial_Out <= XmitReg_s(0);
-------------------------------------------------------------------------------
-- Concurrent signal assignment for XmitMT (transmitter eMpTy)
-- where XmitMT is true if COunt_s is equal to 9.
-------------------------------------------------------------------------------
XmitMT <= true when Count_s = 9
else false;
end UartXmt_Beh;
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