---------------------------------------------------------------
----- Design Unit : ADD_SUB
---------------------------------------------------------------
library VERILOG; use VERILOG.all;
use VERILOG_STD.all;
use STD.TEXTIO.all;
use WORK.all;
---------- Entity Declaration ----------
entity ADD_SUB is
port (
COUT : OUT WIRE;
FBAR : OUT WIRE;
F : OUT WIRE;
S1 : IN WIRE;
B : IN WIRE;
CIN : IN WIRE;
S0 : IN WIRE;
A : IN WIRE
);
signal COUT_temp : WIRE;
signal FBAR_temp : WIRE;
signal F_temp : WIRE;
signal S1_temp : WIRE;
signal B_temp : WIRE;
signal CIN_temp : WIRE;
signal S0_temp : WIRE;
signal A_temp : WIRE;
end ADD_SUB;
---------- Architecture Body ----------
architecture arch_ADD_SUB of ADD_SUB is
component AND_GATE
generic ( strength0 : STRENGTH := STRONG;
strength1 : STRENGTH := STRONG;
delay1 : INTEGER := NOT_SPECIFIED;
delay2 : INTEGER := NOT_SPECIFIED;
N : NATURAL := 2;
delay_units : TIME := 1 ns
);
port ( output : out MVL;
inputs : in MVL_VECTOR (1 TO N)
);
end component;
for all: AND_GATE use entity VERILOG.AND_GATE(ARCH_AND_GATE);
component OR_GATE
generic ( strength0 : STRENGTH := STRONG;
strength1 : STRENGTH := STRONG;
delay1 : INTEGER := NOT_SPECIFIED;
delay2 : INTEGER := NOT_SPECIFIED;
N : NATURAL := 2;
delay_units : TIME := 1 ns
);
port ( output : out MVL;
inputs : in MVL_VECTOR (1 TO N)
);
end component;
for all: OR_GATE use entity VERILOG.OR_GATE(ARCH_OR_GATE);
component NOR_GATE
generic ( strength0 : STRENGTH := STRONG;
strength1 : STRENGTH := STRONG;
delay1 : INTEGER := NOT_SPECIFIED;
delay2 : INTEGER := NOT_SPECIFIED;
N : NATURAL := 2;
delay_units : TIME := 1 ns
);
port ( output : out MVL;
inputs : in MVL_VECTOR (1 TO N)
);
end component;
for all: NOR_GATE use entity VERILOG.NOR_GATE(ARCH_NOR_GATE);
component XNOR_GATE
generic ( strength0 : STRENGTH := STRONG;
strength1 : STRENGTH := STRONG;
delay1 : INTEGER := NOT_SPECIFIED;
delay2 : INTEGER := NOT_SPECIFIED;
N : NATURAL := 2;
delay_units : TIME := 1 ns
);
port ( output : out MVL;
inputs : in MVL_VECTOR (1 TO N)
);
end component;
for all: XNOR_GATE use entity VERILOG.XNOR_GATE(ARCH_XNOR_GATE);
component NOT_GATE
generic ( strength0 : STRENGTH := STRONG;
strength1 : STRENGTH := STRONG;
delay1 : INTEGER := NOT_SPECIFIED;
delay2 : INTEGER := NOT_SPECIFIED;
N : NATURAL := 1;
delay_units : TIME := 1 ns
);
port ( outputs : out MVL_VECTOR (1 TO N);
input : in MVL
);
end component;
for all: NOT_GATE use entity VERILOG.NOT_GATE(ARCH_NOT_GATE);
component BUF_GATE
generic ( strength0 : STRENGTH := STRONG;
strength1 : STRENGTH := STRONG;
delay1 : INTEGER := NOT_SPECIFIED;
delay2 : INTEGER := NOT_SPECIFIED;
N : NATURAL := 1;
delay_units : TIME := 1 ns
);
port ( outputs : out MVL_VECTOR (1 TO N);
input : in MVL
);
end component;
for all: BUF_GATE use entity VERILOG.BUF_GATE(ARCH_BUF_GATE);
signal temp_f1, temp_f2, t_carry3, t_carry2, t_carry1,
S1xnorB, S0xnorA, CIN_buf, temp_sum_bar, CIN_not, temp_sum : WIRE;
begin
TEMP_ASSIGN_1: COUT <= COUT_temp;
TEMP_ASSIGN_2: FBAR <= FBAR_temp;
TEMP_ASSIGN_3: F <= F_temp;
TEMP_ASSIGN_4: S1_temp <= S1;
TEMP_ASSIGN_5: B_temp <= B;
TEMP_ASSIGN_6: CIN_temp <= CIN;
TEMP_ASSIGN_7: S0_temp <= S0;
TEMP_ASSIGN_8: A_temp <= A;
g1: NOR_GATE
generic map (
N => 2
)
port map (
output => FBAR_temp,
inputs(1) => temp_f1,
inputs(2) => temp_f2
)
;
g2: OR_GATE
generic map (
N => 3
)
port map (
output => COUT_temp,
inputs(1) => t_carry3,
inputs(2) => t_carry2,
inputs(3) => t_carry1
)
;
g3: AND_GATE
generic map (
N => 2
)
port map (
output => t_carry1,
inputs(1) => S1xnorB,
inputs(2) => S0xnorA
)
;
g4: AND_GATE
generic map (
N => 2
)
port map (
output => t_carry3,
inputs(1) => CIN_buf,
inputs(2) => S0xnorA
)
;
g5: AND_GATE
generic map (
N => 2
)
port map (
output => t_carry2,
inputs(1) => S1xnorB,
inputs(2) => CIN_buf
)
;
g6: AND_GATE
generic map (
N => 2
)
port map (
output => temp_f1,
inputs(1) => temp_sum_bar,
inputs(2) => CIN_not
)
;
g7: AND_GATE
generic map (
N => 2
)
port map (
output => temp_f2,
inputs(1) => temp_sum,
inputs(2) => CIN_buf
)
;
g8: NOT_GATE
generic map (
N => 1
)
port map (
outputs(1) => F_temp,
input => FBAR_temp
)
;
g9: NOT_GATE
generic map (
N => 1
)
port map (
outputs(1) => temp_sum_bar,
input => temp_sum
)
;
g10: NOT_GATE
generic map (
delay1 => 22,
N => 1
)
port map (
outputs(1) => CIN_not,
input => CIN_temp
)
;
g11: BUF_GATE
generic map (
delay1 => 22,
N => 1
)
port map (
outputs(1) => CIN_buf,
input => CIN_temp
)
;
g12: XNOR_GATE
generic map (
N => 2
)
port map (
output => temp_sum,
inputs(1) => S1xnorB,
inputs(2) => S0xnorA
)
;
g13: XNOR_GATE
generic map (
delay1 => 45,
N => 2
)
port map (
output => S1xnorB,
inputs(1) => S1_temp,
inputs(2) => B_temp
)
;
g14: XNOR_GATE
generic map (
delay1 => 45,
N => 2
)
port map (
output => S0xnorA,
inputs(1) => S0_temp,
inputs(2) => A_temp
)
;
end arch_ADD_SUB;
---------------------------------------------------------------
----- Design Unit : ecl10180
---------------------------------------------------------------
library VERILOG; use VERILOG.all;
use VERILOG_STD.all;
use STD.TEXTIO.all;
use WORK.all;
---------- Entity Declaration ----------
entity ecl10180 is
port (
f0 : OUT WIRE;
f0bar : OUT WIRE;
f1 : OUT WIRE;
f1bar : OUT WIRE;
c0out : OUT WIRE;
c1out : OUT WIRE;
a0 : IN WIRE;
a1 : IN WIRE;
b0 : IN WIRE;
b1 : IN WIRE;
c0in : IN WIRE;
c1in : IN WIRE;
s0 : IN WIRE;
s1 : IN WIRE
);
signal f0_temp : WIRE;
signal f0bar_temp : WIRE;
signal f1_temp : WIRE;
signal f1bar_temp : WIRE;
signal c0out_temp : WIRE;
signal c1out_temp : WIRE;
signal a0_temp : WIRE;
signal a1_temp : WIRE;
signal b0_temp : WIRE;
signal b1_temp : WIRE;
signal c0in_temp : WIRE;
signal c1in_temp : WIRE;
signal s0_temp : WIRE;
signal s1_temp : WIRE;
end ecl10180;
---------- Architecture Body ----------
architecture arch_ecl10180 of ecl10180 is
component ADD_SUB
port (
COUT : OUT WIRE;
FBAR : OUT WIRE;
F : OUT WIRE;
S1 : IN WIRE;
B : IN WIRE;
CIN : IN WIRE;
S0 : IN WIRE;
A : IN WIRE
);
end component;
for all: ADD_SUB use entity WORK.ADD_SUB(arch_ADD_SUB);
begin
TEMP_ASSIGN_1: f0 <= f0_temp;
TEMP_ASSIGN_2: f0bar <= f0bar_temp;
TEMP_ASSIGN_3: f1 <= f1_temp;
TEMP_ASSIGN_4: f1bar <= f1bar_temp;
TEMP_ASSIGN_5: c0out <= c0out_temp;
TEMP_ASSIGN_6: c1out <= c1out_temp;
TEMP_ASSIGN_7: a0_temp <= a0;
TEMP_ASSIGN_8: a1_temp <= a1;
TEMP_ASSIGN_9: b0_temp <= b0;
TEMP_ASSIGN_10: b1_temp <= b1;
TEMP_ASSIGN_11: c0in_temp <= c0in;
TEMP_ASSIGN_12: c1in_temp <= c1in;
TEMP_ASSIGN_13: s0_temp <= s0;
TEMP_ASSIGN_14: s1_temp <= s1;
adder0: ADD_SUB
port map (
c0out_temp,
f0bar_temp,
f0_temp,
s1_temp,
b0_temp,
c0in_temp,
s0_temp,
a0_temp
)
;
adder1: ADD_SUB
port map (
c1out_temp,
f1bar_temp,
f1_temp,
s1_temp,
b1_temp,
c1in_temp,
s0_temp,
a1_temp
)
;
end arch_ecl10180;
---------------------------------------------------------------
----- Design Unit : test10180
---------------------------------------------------------------
library VERILOG; use VERILOG.all;
use VERILOG_STD.all;
use STD.TEXTIO.all;
use WORK.all;
---------- Entity Declaration ----------
entity test10180 is
end test10180;
---------- Architecture Body ----------
architecture arch_test10180 of test10180 is
signal A, B, A_1, B_1 : MVL_VECTOR(1 downto 0) := "XX";
signal S, S_1 : MVL_VECTOR(1 downto 0) := "XX";
signal C, C_1 : MVL := 'X';
signal temp, temp_1 : MVL_VECTOR(1 to 7) := "XXXXXXX";
signal OUT1, OUT2, OUT_BAR1, OUT_BAR2, CARRY1,
CARRY2 : WIRE;
signal a_index, b_index, s_index, a_index_1 : VLINT;
component ecl10180
port (
f0 : OUT WIRE;
f0bar : OUT WIRE;
f1 : OUT WIRE;
f1bar : OUT WIRE;
c0out : OUT WIRE;
c1out : OUT WIRE;
a0 : IN WIRE;
a1 : IN WIRE;
b0 : IN WIRE;
b1 : IN WIRE;
c0in : IN WIRE;
c1in : IN WIRE;
s0 : IN WIRE;
s1 : IN WIRE
);
end component;
for all: ecl10180 use entity WORK.ecl10180(arch_ecl10180);
begin
INITIAL_1: process
variable DISPLAY_1 : LINE;
begin
temp_1 <= align_size ('0', temp'LENGTH);
wait for 0 ns;
a_index_1 <= align_size ('0', a_index'LENGTH);
wait until bool (eq (a_index, a_index_1));
while bool ( lt (a_index, "10000000")) loop
wait for 0 ns;
temp_1 <= align_size (temp + '1', temp'LENGTH);
wait for 0 ns;
A_1(1 downto 0) <= temp(1 to 2);
wait for 0 ns;
B_1(1 downto 0) <= temp(3 to 4);
wait for 0 ns;
S_1(1 downto 0) <= temp(5 to 6);
wait for 0 ns;
C_1 <= temp(7);
wait for 99 ns;
wait for 0 ns;
wait for 0 ns;
write (DISPLAY_1, TIME' (sys_time (1 ns) ), RIGHT, 22);
write (DISPLAY_1, STRING' (" "));
write (DISPLAY_1, MVL_STRING (S(0)));
write (DISPLAY_1, MVL_STRING (S(1)));
write (DISPLAY_1, STRING' (" "));
write (DISPLAY_1, MVL_STRING (A(0)));
write (DISPLAY_1, MVL_STRING (B(0)));
write (DISPLAY_1, MVL_STRING (C));
write (DISPLAY_1, STRING' (" "));
write (DISPLAY_1, MVL_STRING (OUT2));
write (DISPLAY_1, MVL_STRING (OUT_BAR2));
write (DISPLAY_1, MVL_STRING (CARRY2));
write (DISPLAY_1, STRING' (" "));
write (DISPLAY_1, STRING' (" "));
write (DISPLAY_1, MVL_STRING (S(0)));
write (DISPLAY_1, MVL_STRING (S(1)));
write (DISPLAY_1, STRING' (" "));
write (DISPLAY_1, MVL_STRING (A(1)));
write (DISPLAY_1, MVL_STRING (B(1)));
write (DISPLAY_1, MVL_STRING (CARRY2));
write (DISPLAY_1, STRING' (" "));
write (DISPLAY_1, MVL_STRING (OUT1));
write (DISPLAY_1, MVL_STRING (OUT_BAR1));
write (DISPLAY_1, MVL_STRING (CARRY1));
writeline (OUTPUT, DISPLAY_1);
wait for 1 ns;
a_index_1 <= align_size (a_index + '1', a_index'LENGTH);
wait until bool (eq (a_index, a_index_1));
end loop;
sys_finish;
wait;
end process INITIAL_1;
add_sub1: ecl10180
port map (
OUT2,
OUT_BAR2,
OUT1,
OUT_BAR1,
CARRY2,
CARRY1,
A(0),
A(1),
B(0),
B(1),
C,
CARRY2,
S(0),
S(1)
)
;
temp <= temp_1 when not temp_1'quiet else
temp;
a_index <= a_index_1 when not a_index_1'quiet else
a_index;
A <= A_1 when not A_1'quiet else
A;
B <= B_1 when not B_1'quiet else
B;
S <= S_1 when not S_1'quiet else
S;
C <= C_1 when not C_1'quiet else
C;
end arch_test10180;
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