--==========================================================
-- Design units : ELEMpack (package)
--
-- File name : ELEMpack.vhd
--
-- Purpose : ELEMpack contains simple gates and
-- structures of gates
--
-- Limitations : This package has to be compiled in the
-- default library WORK
--
-- Library : WORK
--
-- Dependencies : IEEE
--
-- Author : Hans-Peter Eich, REFT
--
-- Simulator : Synopsys V3.1a on Sun SPARCstation 10
--
-----------------------------------------------------------
-- Revision list
-- Version Author Date Changes
--
-- V1.0 hpe 10.01.95 None
-- V1.1 cjt 06.07.95 Rename of OR2 to OR_2
--=========================================================
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
PACKAGE ELEMpack IS
COMPONENT INV -- inverter
PORT(X: IN std_logic; -- data in
Y: OUT std_logic); -- data out
END COMPONENT;
COMPONENT BUF -- buffer
PORT(X: IN std_logic; -- data in
Y: OUT std_logic); -- data out
END COMPONENT;
COMPONENT nBUF -- n bit buffer
GENERIC(N: POSITIVE); -- structure length
PORT(X: IN std_logic_vector(N-1 DOWNTO 0); -- n bit data in
Y: OUT std_logic_vector(N-1 DOWNTO 0)); -- n bit data out
END COMPONENT;
COMPONENT NAND2 -- nand gate with 2 inputs
PORT(A: IN std_logic; -- data in
B: IN std_logic; -- data in
Y: OUT std_logic); -- data out
END COMPONENT;
COMPONENT NAND3 -- nand gate with 3 inputs
PORT(A: IN std_logic; -- data in
B: IN std_logic; -- data in
C: IN std_logic; -- data in
Y: OUT std_logic); -- data out
END COMPONENT;
COMPONENT AND2 -- and gate with 2 inputs
PORT(A: IN std_logic; -- data in
B: IN std_logic; -- data in
Y: OUT std_logic); -- data out
END COMPONENT;
COMPONENT AND3 -- and gate with 3 inputs
PORT(A: IN std_logic; -- data in
B: IN std_logic; -- data in
C: IN std_logic; -- data in
Y: OUT std_logic); -- data out
END COMPONENT;
COMPONENT AND4 -- and gate with 4 inputs
PORT(A: IN std_logic; -- data in
B: IN std_logic; -- data in
C: IN std_logic; -- data in
D: IN std_logic; -- data in
Y: OUT std_logic); -- data out
END COMPONENT;
COMPONENT AND5 -- and gate with 5 inputs
PORT(A: IN std_logic; -- data in
B: IN std_logic; -- data in
C: IN std_logic; -- data in
D: IN std_logic; -- data in
E: IN std_logic; -- data in
Y: OUT std_logic); -- data out
END COMPONENT;
COMPONENT NOR2 -- nor gate with 2 inputs
PORT(A: IN std_logic; -- data in
B: IN std_logic; -- data in
Y: OUT std_logic); -- data out
END COMPONENT;
COMPONENT NOR3 -- nor gate with 3 inputs
PORT(A: IN std_logic; -- data in
B: IN std_logic; -- data in
C: IN std_logic; -- data in
Y: OUT std_logic); -- data out
END COMPONENT;
COMPONENT OR_2 -- or gate with 2 inputs
PORT(A: IN std_logic; -- data in
B: IN std_logic; -- data in
Y: OUT std_logic); -- data out
END COMPONENT;
COMPONENT OR3 -- or gate with 3 inputs
PORT(A: IN std_logic; -- data in
B: IN std_logic; -- data in
C: IN std_logic; -- data in
Y: OUT std_logic); -- data out
END COMPONENT;
COMPONENT OR4 -- or gate with 4 inputs
PORT(A: IN std_logic; -- data in
B: IN std_logic; -- data in
C: IN std_logic; -- data in
D: IN std_logic; -- data in
Y: OUT std_logic); -- data out
END COMPONENT;
COMPONENT OR5 -- or gate with 5 inputs
PORT(A: IN std_logic; -- data in
B: IN std_logic; -- data in
C: IN std_logic; -- data in
D: IN std_logic; -- data in
E: IN std_logic; -- data in
Y: OUT std_logic); -- data out
END COMPONENT;
COMPONENT NXOR2 -- not exclusive or gate
PORT(A: IN std_logic; -- data in
B: IN std_logic; -- data in
Y: OUT std_logic); -- data out
END COMPONENT;
COMPONENT XOR2 -- exclusive or gate
PORT(A: IN std_logic; -- data in
B: IN std_logic; -- data in
Y: OUT std_logic); -- data out
END COMPONENT;
COMPONENT MUX -- 2:1 multiplexer
PORT(A: IN std_logic; -- data in
B: IN std_logic; -- data in
S: IN std_logic; -- select input
Y: OUT std_logic); -- data out
END COMPONENT;
COMPONENT DMUX -- 1:2 demultiplexer
PORT(X: IN std_logic; -- data in
S: IN std_logic; -- select output
Y0: OUT std_logic; -- data out
Y1: OUT std_logic); -- data out
END COMPONENT;
COMPONENT DL -- delay latch
PORT( D: IN std_logic; -- data in
CLK: IN std_logic; -- clock in
Q: OUT std_logic); -- state out
END COMPONENT;
COMPONENT DFF -- delay flipflop
PORT( D: IN std_logic; -- data in
CLK: IN std_logic; -- clock in
Q: OUT std_logic); -- state out
END COMPONENT;
COMPONENT DFFs -- delay flipflop with enable
PORT( D: IN std_logic; -- data in
S: IN std_logic; -- enable input
CLK: IN std_logic; -- clock in
Q: OUT std_logic; -- state out
QZ: OUT std_logic); -- inverse state out
END COMPONENT;
COMPONENT DFFsr -- delay flipflop with enable and reset
PORT( D: IN std_logic; -- data in
S: IN std_logic; -- enable input
R: IN std_logic; -- asynchronous reset , active low
CLK: IN std_logic; -- clock in
Q: OUT std_logic); -- state out
END COMPONENT;
COMPONENT RSFFR -- rs flipflop with clear
PORT(S: IN std_logic; -- set input
R: IN std_logic; -- reset input
C: IN std_logic; -- clear input
Q: OUT std_logic; -- state out
QZ: OUT std_logic); -- inverse state out
END COMPONENT;
COMPONENT RSFF -- rs flipflop
PORT(S: IN std_logic; -- set input
R: IN std_logic; -- reset input
Q: OUT std_logic; -- state out
QZ: OUT std_logic); -- inverse state out
END COMPONENT;
COMPONENT nMUX -- n bit 2:1 multiplexer
GENERIC(N: POSITIVE);
PORT(A0: IN std_logic_vector(N-1 DOWNTO 0); -- n bit data in
A1: IN std_logic_vector(N-1 DOWNTO 0); -- n bit data in
S: IN std_logic; -- select input
Y: OUT std_logic_vector(N-1 DOWNTO 0)); -- n bit data out
END COMPONENT;
COMPONENT nDMUX -- n bit 1:2 demultiplexer
GENERIC(N: POSITIVE);
PORT(X: IN std_logic_vector(N-1 DOWNTO 0); -- n bit data n
S: IN std_logic; -- select output
Y0: OUT std_logic_vector(N-1 DOWNTO 0); -- n bit data out
Y1: OUT std_logic_vector(N-1 DOWNTO 0)); -- n bit data out
END COMPONENT;
COMPONENT nREG -- n bit register with enable
GENERIC(N: POSITIVE);
PORT(CLK: IN std_logic; -- clock in
S: IN std_logic; -- enable input
X: IN std_logic_vector(N-1 DOWNTO 0); -- n bit data in
Y: OUT std_logic_vector(N-1 DOWNTO 0)); -- n bit data out
END COMPONENT;
COMPONENT nREGr -- n bit register with enable and reset
GENERIC(N: POSITIVE);
PORT(CLK: IN std_logic; -- clock in
S: IN std_logic; -- enable input
R: IN std_logic; -- asynchronous reset, active low
X: IN std_logic_vector(N-1 DOWNTO 0); -- n bit data in
Y: OUT std_logic_vector(N-1 DOWNTO 0)); -- n bit data out
END COMPONENT;
COMPONENT HA -- half adder
PORT(A : IN std_logic; -- data in
B : IN std_logic; -- data in
Sum : OUT std_logic; -- sum out
COUT : OUT std_logic); -- carry out
END COMPONENT;
COMPONENT FA -- full adder
PORT(A : IN std_logic; -- data in
B : IN std_logic; -- data in
CIN : IN std_logic; -- carry in
Sum : OUT std_logic; -- sum out
COUT : OUT std_logic); -- carry out
END COMPONENT;
COMPONENT nINC -- n bit increment
GENERIC(N: POSITIVE);
PORT( X: IN std_logic_vector(N-1 DOWNTO 0); -- n bit data in
Y: OUT std_logic_vector(N-1 DOWNTO 0); -- n bit data out
Cout : OUT std_logic); -- cary out
END COMPONENT;
COMPONENT CRA -- n bit carry ripple adder
GENERIC(N: POSITIVE);
PORT(A: IN std_logic_vector(N-1 DOWNTO 0); -- n bit data in
B: IN std_logic_vector(N-1 DOWNTO 0); -- n bit data out
Cin: IN std_logic; -- carry in
Sum: OUT std_logic_vector(N-1 DOWNTO 0); -- sum out
Cout: OUT std_logic); -- carry out
END COMPONENT;
COMPONENT AddSub -- n bit carry ripple adder or subtractor
GENERIC (N: POSITIVE);
PORT ( A: IN std_logic_vector(N-1 DOWNTO 0); -- n bit data in
B: IN std_logic_vector(N-1 DOWNTO 0); -- n bit data in
Mode: IN std_logic; -- mode 0 add,mode 1 sub
Y: OUT std_logic_vector(N-1 DOWNTO 0); -- n bit data out
Cout: OUT std_logic); -- carry out
END COMPONENT;
COMPONENT nSREG -- n bit shift register
GENERIC(N: POSITIVE);
PORT( X: IN std_logic_vector(N-1 DOWNTO 0); -- n bit data in
S: IN std_logic; -- shift
CLK: IN std_logic; -- clock in
Y: OUT std_logic_vector(N-1 DOWNTO 0)); -- n bit data out
END COMPONENT;
COMPONENT nCMP0 -- test n bit vector on equal zero
GENERIC(N: POSITIVE);
PORT(X: IN std_logic_vector(N-1 DOWNTO 0); -- n bit data in
Y: OUT std_logic); -- equal zero
END COMPONENT;
COMPONENT nCMPN -- compare two n bit vectors
GENERIC(N: POSITIVE);
PORT(A: IN std_logic_vector(N-1 DOWNTO 0); -- n bit data in
B: IN std_logic_vector(N-1 DOWNTO 0); -- n bit data in
eq: OUT std_logic; -- A equals B
ls: OUT std_logic); -- A less B
END COMPONENT;
COMPONENT nLSH -- n bit shift left
GENERIC(N: POSITIVE);
PORT( X: IN std_logic_vector(N-1 DOWNTO 0); -- n bit data in
Cin: IN std_logic; -- carry in
Y: OUT std_logic_vector(N-1 DOWNTO 0); -- n bit data out
Cout: OUT std_logic); -- carry out
END COMPONENT;
COMPONENT nRSH -- n bit shift right
GENERIC(N: POSITIVE);
PORT( X: IN std_logic_vector(N-1 DOWNTO 0); -- n bit data in
Cin: IN std_logic; -- carry in
Y: OUT std_logic_vector(N-1 DOWNTO 0); -- n bit data out
Cout: OUT std_logic); -- carry out
END COMPONENT;
COMPONENT expand -- expand bit vector and fill with zero
GENERIC (N,M: POSITIVE);
PORT (X: IN std_logic_vector(N-1 DOWNTO 0); -- n bit data in
Y: OUT std_logic_vector (M-1 DOWNTO 0)); -- m bit data out
END COMPONENT;
COMPONENT priority -- lowest bit has priority, other bits are suppressed
GENERIC (N: POSITIVE);
PORT (X: IN std_logic_vector(N-1 DOWNTO 0); -- n bit data in
Y: OUT std_logic_vector(N-1 DOWNTO 0)); -- n bit data out
END COMPONENT;
END ELEMpack;
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