--
-- Rcsid[] = "$Id: oprlogic.vhd,v 2.1 1993/10/06 01:04:36 alex Exp $";
--

entity oprlogic is
port(BO7,  BO6,  BO5,  BO4,  BO3,  BO2,  BO1,  BO0: out bit;
	 ALUA,ALUB: out bit_vector(7 downto 0);
     BIN7,BIN6,BIN5,BIN4,BIN3,BIN2,BIN1,BIN0,
	 WRACC,ACCOUTEN,WRAUXACC, WR2TEMP,TEMP_OUT,VCC,GND,CLK,
     T4,T2,AC_buf,CY,CLEAR, ID4,ID7,ID12,ID16,ENBUSTOAUX: in bit);
end;

architecture structure of oprlogic is

component reg8bits
port(Q: out bit_vector(0 to 7);
	 D: in bit_vector(0 to 7);
     CK, WRENABLE, CLEAR, PRESET: in bit);
end component;

component reg_8bit
port(Q: out bit_vector(0 to 7);
	 D: in bit_vector(0 to 7);
     CK, WRENABLE, CLEAR, PRESET: in bit);
end component;

component mux_4bit
port(Y: out bit_vector(0 to 3);
	 A,B: in bit_vector(0 to 3);
	 choose: in bit);
end component;

component ocnand
port(O: out bit_vector(7 downto 0);
     I: in bit_vector(7 downto 0);
     ENABLE: in bit);
end component;

signal temp, ac: bit_vector(0 to 7);
signal mux: bit_vector(0 to 7);
signal n7, n8, n9, n10, n11, n12, n15: bit;
signal DAA, INR : bit;

begin
V0 : REG_8BIT port map(ac(0 to 7),BIN0,BIN1,BIN2,BIN3,BIN4,BIN5,BIN6,BIN7,CLK,WRACC,CLEAR,VCC);
V1 : OCNAND  port map(BO0,BO1,BO2,BO3,BO4,BO5,BO6,BO7,ac(0 to 7),ACCOUTEN);

TEMP_REG : reg8bits port map(temp(0 to 7),BIN0,BIN1,BIN2,BIN3,BIN4,BIN5,BIN6,BIN7,
                             CLK,WR2TEMP,CLEAR,VCC);
--                             CKn,WR2TEMP,CLEAR,VCC);
U1 : OCNAND port map(BO0,BO1,BO2,BO3,BO4,BO5,BO6,BO7,temp(0 to 7),temp_out);

AUX_ACC :  reg_8bit port map(ALUA(0),ALUA(1),ALUA(2),ALUA(3),ALUA(4),ALUA(5),ALUA(6),ALUA(7),
                             mux(0 to 7), CLK,WRAUXACC,CLEAR,VCC);

U3 : mux_4bit port map(mux(0 to 3),ac(0 to 3),BIN0,BIN1,BIN2,BIN3,ENBUSTOAUX);
U4 : mux_4bit port map(mux(4 to 7),ac(4 to 7),BIN4,BIN5,BIN6,BIN7,ENBUSTOAUX);
U5 : mux_4bit port map(ALUB(0),ALUB(1),ALUB(2),ALUB(3),temp(0 to 3),INR,n11,n11,GND,n15);
U6 : mux_4bit port map(ALUB(4),ALUB(5),ALUB(6),ALUB(7),temp(4 to 7),GND,n12,n12,GND,n15);
U7 : and_gate generic map (1,1) port map(n7,ac(1),ac(3));
U8 : nor_gate generic map (1,1) port map(n8,n7,AC_buf);
U9 : and_gate generic map (1,1) port map(n9,ac(5),ac(7));
U10 : nor_gate generic map (1,1) port map(n10,n9,CY);
U11 : nor_gate generic map (1,1) port map(n11,n8,T4,INR);
U12 : nor_gate generic map (1,1) port map(n12,n10,T2,INR);
U13 : nor_gate generic map (1,1) port map(INR,ID16,ID4);
U14 : nor_gate generic map (1,1) port map(DAA,ID16,ID12,ID7);
U15 : or_gate generic map (1,1) port map(n15,DAA,INR);
end structure;

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