| | | | | | |
_________________
-| |-
-| |-
-| |-
-| CYPRESS |-
-| |-
-| |- Warp VHDL Synthesis Compiler: Version 4 IR x95
-| |- Copyright (C) 1991, 1992, 1993,
|_______________| 1994, 1995, 1996, 1997, 1998 Cypress Semiconductor
| | | | | | |
======================================================================
Compiling: adder4.vhd
Options: -d c22v10 -v1 -o2 -fo adder4.vhd
======================================================================
vhdlfe V4 IR x95: VHDL parser
Tue Dec 21 11:33:24 1999
Library 'work' => directory 'lc22v10'
Linking '/opt/ecad/warp/lib/common/work/cypress.vif'.
Library 'ieee' => directory '/opt/ecad/warp/lib/ieee/work'
Linking '/opt/ecad/warp/lib/ieee/work/stdlogic.vif'.
vhdlfe: No errors.
tovif V4 IR x95: High-level synthesis
Tue Dec 21 11:33:25 1999
Linking '/opt/ecad/warp/lib/common/work/cypress.vif'.
Linking '/opt/ecad/warp/lib/ieee/work/stdlogic.vif'.
tovif: No errors.
topld V4 IR x95: Synthesis and optimization
Tue Dec 21 11:33:26 1999
Linking '/opt/ecad/warp/lib/common/work/cypress.vif'.
Linking '/opt/ecad/warp/lib/ieee/work/stdlogic.vif'.
----------------------------------------------------------
Detecting unused logic.
----------------------------------------------------------
------------------------------------------------------
Alias Detection
------------------------------------------------------
------------------------------------------------------
Aliased 0 equations, 1 wires.
------------------------------------------------------
----------------------------------------------------------
Circuit simplification
----------------------------------------------------------
Note: Virtual signal c_1 with ( cost: 56 or cost_inv: 8) > 30 or with size: 3 > 58 has been made a (soft) node.
Note: Virtual signal c_2 with ( cost: 56 or cost_inv: 8) > 30 or with size: 3 > 58 has been made a (soft) node.
Note: Virtual signal c_3 with ( cost: 56 or cost_inv: 8) > 30 or with size: 3 > 58 has been made a (soft) node.
----------------------------------------------------------
Circuit simplification results:
Expanded 0 signals.
Turned 3 signals into soft nodes.
Maximum expansion cost was set at 1.
----------------------------------------------------------
Created 18 PLD nodes.
topld: No errors.
----------------------------------------------------------------------------
PLD Optimizer Software: DSGNOPT.EXE 11/NOV/97 [v4.02 ] 4 IR x95
DESIGN HEADER INFORMATION (11:33:26)
Input File(s): adder4.pla
Device : C22V10
ReportFile : adder4.rpt
Program Controls:
None.
Signal Requests:
GROUP DT-OPT ALL
GROUP FAST_SLEW ALL
GROUP SOFT c_1 c_2 c_3
Completed Successfully
----------------------------------------------------------------------------
PLD Optimizer Software: DSGNOPT.EXE 11/NOV/97 [v4.02 ] 4 IR x95
OPTIMIZATION OPTIONS (11:33:26)
Messages:
Information: Process virtual 'c_1' ... converted to NODE.
... converted to NODE.
... converted to NODE.
Information: Optimizing logic using best output polarity for signals:
cout sum_0 sum_1 sum_2 sum_3 c_1 c_2 c_3
Summary:
Error Count = 0 Warning Count = 0
Completed Successfully
----------------------------------------------------------------------------
PLD Optimizer Software: MINOPT.EXE 11/NOV/97 [v4.02 ] 4 IR x95
LOGIC MINIMIZATION (11:33:26)
Messages:
Summary:
Error Count = 0 Warning Count = 0
Completed Successfully
----------------------------------------------------------------------------
PLD Optimizer Software: DSGNOPT.EXE 11/NOV/97 [v4.02 ] 4 IR x95
OPTIMIZATION OPTIONS (11:33:26)
Messages:
Information: Optimizing Banked Preset/Reset requirements.
Summary:
Error Count = 0 Warning Count = 0
Completed Successfully
----------------------------------------------------------------------------
PLD Compiler Software: PLA2JED.EXE 11/NOV/97 [v4.02 ] 4 IR x95
DESIGN EQUATIONS (11:33:27)
cout =
b_3 * c_3
+ a_3 * c_3
+ a_3 * b_3
sum_0 =
a_0 * /b_0 * /cin
+ /a_0 * b_0 * /cin
+ /a_0 * /b_0 * cin
+ a_0 * b_0 * cin
sum_1 =
a_1 * /b_1 * /c_1
+ /a_1 * b_1 * /c_1
+ /a_1 * /b_1 * c_1
+ a_1 * b_1 * c_1
sum_2 =
a_2 * /b_2 * /c_2
+ /a_2 * b_2 * /c_2
+ /a_2 * /b_2 * c_2
+ a_2 * b_2 * c_2
sum_3 =
a_3 * /b_3 * /c_3
+ /a_3 * b_3 * /c_3
+ /a_3 * /b_3 * c_3
+ a_3 * b_3 * c_3
c_2 =
b_1 * c_1
+ a_1 * c_1
+ a_1 * b_1
c_1 =
b_0 * cin
+ a_0 * cin
+ a_0 * b_0
c_3 =
b_2 * c_2
+ a_2 * c_2
+ a_2 * b_2
Completed Successfully
----------------------------------------------------------------------------
PLD Compiler Software: PLA2JED.EXE 11/NOV/97 [v4.02 ] 4 IR x95
DESIGN RULE CHECK (11:33:27)
Messages:
None.
Summary:
Error Count = 0 Warning Count = 0
Completed Successfully
----------------------------------------------------------------------------
PLD Compiler Software: PLA2JED.EXE 11/NOV/97 [v4.02 ] 4 IR x95
DESIGN SIGNAL PLACEMENT (11:33:27)
Messages:
Information: Checking for duplicate NODE logic.
None.
C22V10
__________________________________________
not used *| 1| |24|* not used
a_3 =| 2| |23|= (c_1)
a_2 =| 3| |22|= sum_3
a_1 =| 4| |21|= sum_2
a_0 =| 5| |20|= sum_1
b_3 =| 6| |19|= sum_0
b_2 =| 7| |18|= cout
b_1 =| 8| |17|* not used
b_0 =| 9| |16|* not used
cin =|10| |15|= (c_3)
not used *|11| |14|= (c_2)
not used *|12| |13|* not used
__________________________________________
Summary:
Error Count = 0 Warning Count = 0
Completed Successfully
----------------------------------------------------------------------------
PLD Compiler Software: PLA2JED.EXE 11/NOV/97 [v4.02 ] 4 IR x95
RESOURCE ALLOCATION (11:33:27)
Information: Macrocell Utilization.
Description Used Max
______________________________________
| Dedicated Inputs | 9 | 11 |
| Clock/Inputs | 0 | 1 |
| I/O Macrocells | 8 | 10 |
______________________________________
17 / 22 = 77 %
Information: Output Logic Product Term Utilization.
Node# Output Signal Name Used Max
________________________________________
| 14 | c_2 | 3 | 8 |
| 15 | c_3 | 3 | 10 |
| 16 | Unused | 0 | 12 |
| 17 | Unused | 0 | 14 |
| 18 | cout | 3 | 16 |
| 19 | sum_0 | 4 | 16 |
| 20 | sum_1 | 4 | 14 |
| 21 | sum_2 | 4 | 12 |
| 22 | sum_3 | 4 | 10 |
| 23 | c_1 | 3 | 8 |
| 25 | Unused | 0 | 1 |
________________________________________
28 / 121 = 23 %
Completed Successfully
----------------------------------------------------------------------------
PLD Compiler Software: PLA2JED.EXE 11/NOV/97 [v4.02 ] 4 IR x95
JEDEC ASSEMBLE (11:33:27)
Messages:
Information: Output file 'adder4.jed' created.
Summary:
Error Count = 0 Warning Count = 0
Completed Successfully at 11:33:27
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