--
-- Dalton Project
-- Tony Givargis, Rilesh Patel, Deepa Varghese, Roman Lysecky, Puneet Mehra
-- 12/29/98
-- Modified on 7/23/99 - Bridge 0 and Bridge 2 added.
-- Version 1.2
--
--*************************************************************************--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
--*************************************************************************--
entity BRIDGE is
generic(START_ADDR : INTEGER := 512);
port( rst : in STD_LOGIC;
clk : in STD_LOGIC;
data : inout UNSIGNED(31 downto 0);
addr : in UNSIGNED(22 downto 0);
rd : in STD_LOGIC;
wr : in STD_LOGIC;
rdy : out STD_LOGIC;
pdata : inout UNSIGNED(7 downto 0);
paddr : out UNSIGNED(22 downto 0);
ior : out STD_LOGIC;
iow : out STD_LOGIC;
ale : out STD_LOGIC;
iochrdy : in STD_LOGIC);
end BRIDGE;
--*************************************************************************--
--*************************************************************************--
architecture BHV_BRIDGE_1 of BRIDGE is
--
-- type declarations
--
type STATE_TYPE is (IDLE_S, READ_S, READWAIT_S, WRITE_S, WRITEWAIT_S);
type ISA_STATE_TYPE is (IDLE_ISA_S, WAIT1_R_S, WAIT2_R_S, CHKRDY_R_S,
WAIT1_W_S, WAIT2_W_S, CHKRDY_W_S);
type ISA_MUX_STATE_TYPE is (IDLE_ISA_MUX_S, DATA1_MUX_R_S, DATA2_MUX_R_S,
DATA3_MUX_R_S, DATA4_MUX_R_S, DATA1_MUX_W_S,
DATA2_MUX_W_S, DATA3_MUX_W_S, DATA4_MUX_W_S,
WAIT1_MUX_R_S, WAIT2_MUX_R_S, WAIT3_MUX_R_S,
WAIT4_MUX_R_S, WAIT1_MUX_W_S, WAIT2_MUX_W_S,
WAIT3_MUX_W_S, WAIT4_MUX_W_S );
--
-- constant declarations
--
constant Z_32 : UNSIGNED(31 downto 0) :=
"ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
constant C1_32 : UNSIGNED(31 downto 0) :=
"00000000000000000000000000000001";
constant C0_32 : UNSIGNED(31 downto 0) :=
"00000000000000000000000000000000";
constant C0_23 : UNSIGNED(22 downto 0) :=
"00000000000000000000000";
constant Z_8 : UNSIGNED(7 downto 0) :=
"ZZZZZZZZ";
constant C0_8 : UNSIGNED(7 downto 0) :=
"00000000";
--
-- signal declarations
--
signal isa_addr, isa_addr2 : UNSIGNED(22 downto 0);
signal isa_data, isa_data2, isa_data_read : UNSIGNED(31 downto 0);
signal isa_data_8, isa_data_read_8 : UNSIGNED(7 downto 0);
signal write_done, read_done, isa_rd, isa_wr : STD_LOGIC;
signal write_done_8, read_done_8, isa_rd_8, isa_wr_8 : STD_LOGIC;
signal state : STATE_TYPE;
signal isa_state : ISA_STATE_TYPE;
signal isa_mux_state : ISA_MUX_STATE_TYPE;
begin
--
-- communicate with high speed bus
--
process(rst,clk)
begin
if(rst = '1') then
--
-- steady state
--
data <= Z_32;
rdy <= '1';
isa_addr <= C0_23;
isa_addr2 <= C0_23;
isa_data <= C0_32;
isa_data2 <= C0_32;
isa_rd <= '0';
isa_wr <= '0';
state <= IDLE_S;
elsif(clk'event and clk = '1') then
--
-- steady state
--
data <= Z_32;
rdy <= '1';
isa_rd <= '0';
isa_wr <= '0';
case state is
when IDLE_S =>
if( rd = '1' ) then
if( conv_integer(addr) >= START_ADDR ) then
isa_addr <= addr;
isa_rd <= '1';
rdy <= '0';
state <= READ_S;
end if;
elsif( wr = '1' ) then
if( conv_integer(addr) >= START_ADDR ) then
isa_addr <= addr;
isa_data <= data;
isa_wr <= '1';
state <= WRITE_S;
end if;
else
state <= IDLE_S;
end if;
when READ_S =>
rdy <= '0';
if( read_done = '1' ) then
data <= isa_data_read;
rdy <= '1';
state <= IDLE_S;
else
state <= READ_S;
end if;
when READWAIT_S =>
rdy <= '0';
if( write_done = '1' ) then
isa_addr <= isa_addr2;
isa_rd <= '1';
state <= READ_S;
else
state <= READWAIT_S;
end if;
when WRITE_S =>
if( write_done = '1' ) then
if( rd = '1' ) then
if( conv_integer(addr) >= START_ADDR ) then
isa_addr <= addr;
isa_rd <= '1';
rdy <= '0';
state <= READ_S;
else
state <= IDLE_S;
end if;
elsif( wr = '1' ) then
if( conv_integer(addr) > START_ADDR ) then
isa_addr <= addr;
isa_data <= data;
isa_wr <= '1';
state <= WRITE_S;
else
state <= IDLE_S;
end if;
else
state <= IDLE_S;
end if;
else
if( rd = '1' ) then
if( conv_integer(addr) >= START_ADDR ) then
isa_addr2 <= addr;
state <= READWAIT_S;
rdy <= '0';
end if;
elsif( wr = '1' ) then
if( conv_integer(addr) > START_ADDR ) then
isa_addr2 <= addr;
isa_data2 <= data;
rdy <= '0';
state <= WRITEWAIT_S;
end if;
else
state <= WRITE_S;
end if;
end if;
when WRITEWAIT_S =>
rdy <= '0';
if( write_done = '1' ) then
isa_addr <= isa_addr2;
isa_data <= isa_data2;
isa_wr <= '1';
state <= WRITE_S;
else
state <= WRITEWAIT_S;
end if;
when others =>
state <= IDLE_S;
end case;
end if;
end process;
--
-- ISA Mux Process
--
process(clk, rst)
begin
if( rst = '1' ) then
read_done <= '0';
write_done <= '0';
isa_rd_8 <= '0';
isa_wr_8 <= '0';
isa_data_read <= C0_32;
isa_mux_state <= IDLE_ISA_MUX_S;
elsif( clk'event and clk='1' ) then
--
-- steady state
--
read_done <= '0';
write_done <= '0';
isa_rd_8 <= '0';
isa_wr_8 <= '0';
case isa_mux_state is
when IDLE_ISA_MUX_S =>
if( isa_rd = '1' ) then
isa_mux_state <= DATA1_MUX_R_S;
elsif( isa_wr = '1' ) then
isa_mux_state <= DATA1_MUX_W_S;
else
isa_mux_state <= IDLE_ISA_MUX_S;
end if;
when DATA1_MUX_R_S =>
isa_rd_8 <= '1';
isa_mux_state <= WAIT1_MUX_R_S;
when WAIT1_MUX_R_S =>
if( read_done_8 = '1' ) then
isa_data_read(7 downto 0) <= isa_data_read_8;
isa_mux_state <= DATA2_MUX_R_S;
else
isa_mux_state <= WAIT1_MUX_R_S;
end if;
when DATA2_MUX_R_S =>
isa_rd_8 <= '1';
isa_mux_state <= WAIT2_MUX_R_S;
when WAIT2_MUX_R_S =>
if( read_done_8 = '1' ) then
isa_data_read(15 downto 8) <= isa_data_read_8;
isa_mux_state <= DATA3_MUX_R_S;
else
isa_mux_state <= WAIT2_MUX_R_S;
end if;
when DATA3_MUX_R_S =>
isa_rd_8 <= '1';
isa_mux_state <= WAIT3_MUX_R_S;
when WAIT3_MUX_R_S =>
if( read_done_8 = '1' ) then
isa_data_read(23 downto 16) <= isa_data_read_8;
isa_mux_state <= DATA4_MUX_R_S;
else
isa_mux_state <= WAIT3_MUX_R_S;
end if;
when DATA4_MUX_R_S =>
isa_rd_8 <= '1';
isa_mux_state <= WAIT4_MUX_R_S;
when WAIT4_MUX_R_S =>
if( read_done_8 = '1' ) then
isa_data_read(31 downto 24) <= isa_data_read_8;
read_done <= '1';
isa_mux_state <= IDLE_ISA_MUX_S;
else
isa_mux_state <= WAIT4_MUX_R_S;
end if;
when DATA1_MUX_W_S =>
isa_wr_8 <= '1';
isa_data_8 <= isa_data(7 downto 0);
isa_mux_state <= WAIT1_MUX_W_S;
when WAIT1_MUX_W_S =>
if( write_done_8 = '1' ) then
isa_mux_state <= DATA2_MUX_W_S;
else
isa_mux_state <= WAIT1_MUX_W_S;
end if;
when DATA2_MUX_W_S =>
isa_wr_8 <= '1';
isa_data_8 <= isa_data(15 downto 8);
isa_mux_state <= WAIT2_MUX_W_S;
when WAIT2_MUX_W_S =>
if( write_done_8 = '1' ) then
isa_mux_state <= DATA3_MUX_W_S;
else
isa_mux_state <= WAIT2_MUX_W_S;
end if;
when DATA3_MUX_W_S =>
isa_wr_8 <= '1';
isa_data_8 <= isa_data(23 downto 16);
isa_mux_state <= WAIT3_MUX_W_S;
when WAIT3_MUX_W_S =>
if( write_done_8 = '1' ) then
isa_mux_state <= DATA4_MUX_W_S;
else
isa_mux_state <= WAIT3_MUX_W_S;
end if;
when DATA4_MUX_W_S =>
isa_wr_8 <= '1';
isa_data_8 <= isa_data(31 downto 24);
isa_mux_state <= WAIT4_MUX_W_S;
when WAIT4_MUX_W_S =>
if( write_done_8 = '1' ) then
write_done <= '1';
isa_mux_state <= IDLE_ISA_MUX_S;
else
isa_mux_state <= WAIT4_MUX_W_S;
end if;
when others =>
isa_mux_state <= IDLE_ISA_MUX_S;
end case;
end if;
end process;
--
-- ISA process
--
process(clk, rst)
begin
if( rst = '1' ) then
pdata <= Z_8;
paddr <= C0_23;
ior <= '0';
iow <= '0';
ale <= '0';
read_done_8 <= '0';
write_done_8 <= '0';
isa_data_read_8 <= C0_8;
isa_state <= IDLE_ISA_S;
elsif(clk'event and clk = '1') then
--
-- steady state
--
pdata <= Z_8;
paddr <= C0_23;
ior <= '0';
iow <= '0';
ale <= '0';
read_done_8 <= '0';
write_done_8 <= '0';
case isa_state is
when IDLE_ISA_S =>
if( isa_rd_8 = '1' ) then
ale <= '1';
paddr <= isa_addr;
isa_state <= WAIT1_R_S;
elsif( isa_wr_8 = '1' ) then
ale <= '1';
paddr <= isa_addr;
isa_state <= WAIT1_W_S;
else
isa_state <= IDLE_ISA_S;
end if;
when WAIT1_R_S =>
paddr <= isa_addr;
ior <= '1';
isa_state <= WAIT2_R_S;
when WAIT2_R_S =>
paddr <= isa_addr;
ior <= '1';
isa_state <= CHKRDY_R_S;
when CHKRDY_R_S =>
paddr <= isa_addr;
ior <= '1';
if(iochrdy = '1') then
read_done_8 <= '1';
isa_data_read_8 <= pdata;
isa_state <= IDLE_ISA_S;
else
isa_state <= CHKRDY_R_S;
end if;
when WAIT1_W_S =>
paddr <= isa_addr;
pdata <= isa_data_8;
iow <= '1';
isa_state <= WAIT2_W_S;
when WAIT2_W_S =>
paddr <= isa_addr;
pdata <= isa_data_8;
iow <= '1';
isa_state <= CHKRDY_W_S;
when CHKRDY_W_S =>
paddr <= isa_addr;
pdata <= isa_data_8;
iow <= '1';
if(iochrdy = '1') then
write_done_8 <= '1';
isa_state <= IDLE_ISA_S;
else
isa_state <= CHKRDY_W_S;
end if;
when others =>
isa_state <= IDLE_ISA_S;
end case;
end if;
end process;
end BHV_BRIDGE_1;
--*************************************************************************--
configuration CFG_BRIDGE1 of BRIDGE is
for BHV_BRIDGE_1
end for;
end CFG_BRIDGE1;
-- end of file --
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