library IEEE,lsi_10k;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_textio.all;
use lsi_10k.COMPONENTS.all;
package CONV_PACK_ISA is
-- define attributes
attribute ENUM_ENCODING : STRING;
end CONV_PACK_ISA;
library IEEE,lsi_10k;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_textio.all;
use lsi_10k.COMPONENTS.all;
use work.CONV_PACK_ISA.all;
entity controller is
port( ctrl_clk, ctrl_rst, IOR, IOW, ALE, WE_m, RE_m : in std_logic; Ald,
Dld, Dst : out std_logic);
end controller;
architecture SYN of controller is
component AO4
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component ND2
port( A, B : in std_logic; Z : out std_logic);
end component;
component AN3
port( A, B, C : in std_logic; Z : out std_logic);
end component;
component NR2
port( A, B : in std_logic; Z : out std_logic);
end component;
component IV
port( A : in std_logic; Z : out std_logic);
end component;
component EON1
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component AO2
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component AO6
port( A, B, C : in std_logic; Z : out std_logic);
end component;
component AN2
port( A, B : in std_logic; Z : out std_logic);
end component;
component FD2P
port( D, CP, CD : in std_logic; Q, QN : out std_logic);
end component;
component IVA
port( A : in std_logic; Z : out std_logic);
end component;
signal nState_2_port, nState_1_port, cState_1_port, nState_0_port,
cState_2_port, cState_0_port, n56, n75, n76, n77, n78, n79, n80, n81, n82
, n83, n84, n85, n86, n87, n88, n89, n90, n91, n92, n93, n94, n95, n96 :
std_logic;
begin
U36 : AO4 port map( A => n56, B => n75, C => n76, D => n77, Z =>
nState_2_port);
U37 : AO4 port map( A => cState_2_port, B => n78, C => IOR, D => n56, Z =>
nState_1_port);
U38 : ND2 port map( A => n79, B => n80, Z => nState_0_port);
U39 : AN3 port map( A => cState_2_port, B => n81, C => cState_1_port, Z =>
Dst);
U40 : AN3 port map( A => cState_2_port, B => n82, C => n81, Z => Dld);
U41 : AO4 port map( A => cState_2_port, B => n56, C => cState_0_port, D =>
n76, Z => Ald);
U42 : NR2 port map( A => n83, B => n84, Z => n78);
U43 : IV port map( A => cState_1_port, Z => n82);
U44 : IV port map( A => cState_0_port, Z => n81);
U45 : IV port map( A => IOW, Z => n85);
U46 : ND2 port map( A => cState_1_port, B => n75, Z => n76);
U47 : NR2 port map( A => n81, B => cState_1_port, Z => n83);
U48 : IV port map( A => cState_2_port, Z => n75);
U49 : ND2 port map( A => RE_m, B => n87, Z => n86);
U50 : EON1 port map( A => n85, B => n81, C => n86, D => n81, Z => n77);
U51 : AO2 port map( A => n85, B => cState_0_port, C => n88, D => n81, Z =>
n84);
U52 : AO6 port map( A => n86, B => n87, C => n76, Z => n89);
U53 : NR2 port map( A => n85, B => n76, Z => n90);
U54 : AN2 port map( A => n83, B => IOR, Z => n91);
U55 : AN3 port map( A => n81, B => n82, C => ALE, Z => n92);
U56 : IV port map( A => WE_m, Z => n87);
U57 : IV port map( A => n83, Z => n56);
U58 : ND2 port map( A => cState_1_port, B => n86, Z => n88);
U59 : AO2 port map( A => n90, B => cState_0_port, C => n89, D => n81, Z =>
n80);
U60 : AO2 port map( A => n91, B => cState_2_port, C => n92, D => n75, Z =>
n79);
cState_reg_0_label : FD2P port map( D => nState_0_port, CP => ctrl_clk, CD
=> n93, Q => cState_0_port, QN => n94);
cState_reg_1_label : FD2P port map( D => nState_1_port, CP => ctrl_clk, CD
=> n93, Q => cState_1_port, QN => n95);
cState_reg_2_label : FD2P port map( D => nState_2_port, CP => ctrl_clk, CD
=> n93, Q => cState_2_port, QN => n96);
U61 : IVA port map( A => ctrl_rst, Z => n93);
end SYN;
library IEEE,lsi_10k;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_textio.all;
use lsi_10k.COMPONENTS.all;
use work.CONV_PACK_ISA.all;
entity comparator is
port( addr_ld : in std_logic; addr_in : in std_logic_vector (0 to 15);
w_match, r_match : out std_logic);
end comparator;
architecture SYN of comparator is
component AN2
port( A, B : in std_logic; Z : out std_logic);
end component;
component NR3
port( A, B, C : in std_logic; Z : out std_logic);
end component;
component ND4
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component IV
port( A : in std_logic; Z : out std_logic);
end component;
component NR2
port( A, B : in std_logic; Z : out std_logic);
end component;
component NR4
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component AN3
port( A, B, C : in std_logic; Z : out std_logic);
end component;
signal n150, n151, n152, n153, n154, n155, n156, n157 : std_logic;
begin
U36 : AN2 port map( A => addr_ld, B => n150, Z => w_match);
U37 : NR3 port map( A => n151, B => n150, C => n152, Z => r_match);
U38 : ND4 port map( A => n153, B => n154, C => n155, D => n156, Z => n152);
U39 : IV port map( A => addr_ld, Z => n151);
U40 : NR2 port map( A => addr_in(15), B => n152, Z => n150);
U41 : NR4 port map( A => addr_in(1), B => addr_in(3), C => addr_in(4), D =>
addr_in(5), Z => n156);
U42 : NR4 port map( A => addr_in(6), B => addr_in(7), C => addr_in(8), D =>
addr_in(9), Z => n155);
U43 : NR4 port map( A => addr_in(10), B => addr_in(11), C => addr_in(12), D
=> addr_in(13), Z => n154);
U44 : AN3 port map( A => addr_in(2), B => n157, C => addr_in(0), Z => n153);
U45 : IV port map( A => addr_in(14), Z => n157);
end SYN;
library IEEE,lsi_10k;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_textio.all;
use lsi_10k.COMPONENTS.all;
use work.CONV_PACK_ISA.all;
entity adder_DW01_add_8_0 is
port( A, B : in std_logic_vector (0 to 7); CI : in std_logic; SUM : out
std_logic_vector (0 to 7); CO : out std_logic);
end adder_DW01_add_8_0;
architecture SYN of adder_DW01_add_8_0 is
component AN2
port( A, B : in std_logic; Z : out std_logic);
end component;
component EO
port( A, B : in std_logic; Z : out std_logic);
end component;
component FA1AP
port( CI, A, B : in std_logic; S, CO : out std_logic);
end component;
signal carry_4_port, carry_2_port, carry_6_port, carry_7_port, carry_3_port,
carry_5_port, carry_1_port, n3 : std_logic;
begin
U4 : AN2 port map( A => A(7), B => B(7), Z => carry_1_port);
U5 : EO port map( A => B(7), B => A(7), Z => SUM(7));
U1_1 : FA1AP port map( CI => carry_1_port, A => A(6), B => B(6), S => SUM(6)
, CO => carry_2_port);
U1_6 : FA1AP port map( CI => carry_6_port, A => A(1), B => B(1), S => SUM(1)
, CO => carry_7_port);
U1_7 : FA1AP port map( CI => carry_7_port, A => A(0), B => B(0), S => SUM(0)
, CO => n3);
U1_2 : FA1AP port map( CI => carry_2_port, A => A(5), B => B(5), S => SUM(5)
, CO => carry_3_port);
U1_3 : FA1AP port map( CI => carry_3_port, A => A(4), B => B(4), S => SUM(4)
, CO => carry_4_port);
U1_4 : FA1AP port map( CI => carry_4_port, A => A(3), B => B(3), S => SUM(3)
, CO => carry_5_port);
U1_5 : FA1AP port map( CI => carry_5_port, A => A(2), B => B(2), S => SUM(2)
, CO => carry_6_port);
end SYN;
library IEEE,lsi_10k;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_textio.all;
use lsi_10k.COMPONENTS.all;
use work.CONV_PACK_ISA.all;
entity adder is
port( num1, num2 : in std_logic_vector (0 to 7); sum : out std_logic_vector
(0 to 7));
end adder;
architecture SYN of adder is
component adder_DW01_add_8_0
port( A, B : in std_logic_vector (0 to 7); CI : in std_logic; SUM : out
std_logic_vector (0 to 7); CO : out std_logic);
end component;
signal n48, n49 : std_logic;
begin
add_23_plus_plus : adder_DW01_add_8_0 port map( A(0) => num1(0), A(1) =>
num1(1), A(2) => num1(2), A(3) => num1(3), A(4) =>
num1(4), A(5) => num1(5), A(6) => num1(6), A(7) =>
num1(7), B(0) => num2(0), B(1) => num2(1), B(2) =>
num2(2), B(3) => num2(3), B(4) => num2(4), B(5) =>
num2(5), B(6) => num2(6), B(7) => num2(7), CI => n48
, SUM(0) => sum(0), SUM(1) => sum(1), SUM(2) =>
sum(2), SUM(3) => sum(3), SUM(4) => sum(4), SUM(5)
=> sum(5), SUM(6) => sum(6), SUM(7) => sum(7), CO =>
n49);
n48 <= '0';
end SYN;
library IEEE,lsi_10k;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_textio.all;
use lsi_10k.COMPONENTS.all;
use work.CONV_PACK_ISA.all;
entity data_reg_0 is
port( clock, reset, load : in std_logic; data_in : in std_logic_vector (0
to 7); data_out : out std_logic_vector (0 to 7));
end data_reg_0;
architecture SYN of data_reg_0 is
component FJK2SP
port( J, K, CP, CD, TI, TE : in std_logic; Q, QN : out std_logic);
end component;
component IVA
port( A : in std_logic; Z : out std_logic);
end component;
signal n57, n58, n59, n60, n61, n62, n63, n64, n65, n66, n67, n68, n69, n70,
n71, n72, n73 : std_logic;
begin
data_out_reg_7_label : FJK2SP port map( J => n57, K => n57, CP => clock, CD
=> n64, TI => data_in(0), TE => load, Q =>
data_out(0), QN => n66);
n57 <= '0';
data_out_reg_6_label : FJK2SP port map( J => n58, K => n58, CP => clock, CD
=> n64, TI => data_in(1), TE => load, Q =>
data_out(1), QN => n67);
n58 <= '0';
data_out_reg_5_label : FJK2SP port map( J => n59, K => n59, CP => clock, CD
=> n64, TI => data_in(2), TE => load, Q =>
data_out(2), QN => n68);
n59 <= '0';
data_out_reg_4_label : FJK2SP port map( J => n60, K => n60, CP => clock, CD
=> n64, TI => data_in(3), TE => load, Q =>
data_out(3), QN => n69);
n60 <= '0';
data_out_reg_3_label : FJK2SP port map( J => n61, K => n61, CP => clock, CD
=> n64, TI => data_in(4), TE => load, Q =>
data_out(4), QN => n70);
n61 <= '0';
data_out_reg_2_label : FJK2SP port map( J => n62, K => n62, CP => clock, CD
=> n64, TI => data_in(5), TE => load, Q =>
data_out(5), QN => n71);
n62 <= '0';
data_out_reg_1_label : FJK2SP port map( J => n63, K => n63, CP => clock, CD
=> n64, TI => data_in(6), TE => load, Q =>
data_out(6), QN => n72);
n63 <= '0';
data_out_reg_0_label : FJK2SP port map( J => n65, K => n65, CP => clock, CD
=> n64, TI => data_in(7), TE => load, Q =>
data_out(7), QN => n73);
U35 : IVA port map( A => reset, Z => n64);
n65 <= '0';
end SYN;
library IEEE,lsi_10k;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_textio.all;
use lsi_10k.COMPONENTS.all;
use work.CONV_PACK_ISA.all;
entity data_reg_1 is
port( clock, reset, load : in std_logic; data_in : in std_logic_vector (0
to 7); data_out : out std_logic_vector (0 to 7));
end data_reg_1;
architecture SYN of data_reg_1 is
component FJK2SP
port( J, K, CP, CD, TI, TE : in std_logic; Q, QN : out std_logic);
end component;
component IVA
port( A : in std_logic; Z : out std_logic);
end component;
signal n66, n67, n68, n69, n70, n71, n72, n73, n74, n75, n76, n77, n78, n79,
n80, n81, n82 : std_logic;
begin
data_out_reg_7_label : FJK2SP port map( J => n66, K => n66, CP => clock, CD
=> n73, TI => data_in(0), TE => load, Q =>
data_out(0), QN => n75);
n66 <= '0';
data_out_reg_6_label : FJK2SP port map( J => n67, K => n67, CP => clock, CD
=> n73, TI => data_in(1), TE => load, Q =>
data_out(1), QN => n76);
n67 <= '0';
data_out_reg_5_label : FJK2SP port map( J => n68, K => n68, CP => clock, CD
=> n73, TI => data_in(2), TE => load, Q =>
data_out(2), QN => n77);
n68 <= '0';
data_out_reg_4_label : FJK2SP port map( J => n69, K => n69, CP => clock, CD
=> n73, TI => data_in(3), TE => load, Q =>
data_out(3), QN => n78);
n69 <= '0';
data_out_reg_3_label : FJK2SP port map( J => n70, K => n70, CP => clock, CD
=> n73, TI => data_in(4), TE => load, Q =>
data_out(4), QN => n79);
n70 <= '0';
data_out_reg_2_label : FJK2SP port map( J => n71, K => n71, CP => clock, CD
=> n73, TI => data_in(5), TE => load, Q =>
data_out(5), QN => n80);
n71 <= '0';
data_out_reg_1_label : FJK2SP port map( J => n72, K => n72, CP => clock, CD
=> n73, TI => data_in(6), TE => load, Q =>
data_out(6), QN => n81);
n72 <= '0';
data_out_reg_0_label : FJK2SP port map( J => n74, K => n74, CP => clock, CD
=> n73, TI => data_in(7), TE => load, Q =>
data_out(7), QN => n82);
U35 : IVA port map( A => reset, Z => n73);
n74 <= '0';
end SYN;
library IEEE,lsi_10k;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_textio.all;
use lsi_10k.COMPONENTS.all;
use work.CONV_PACK_ISA.all;
entity datapath is
port( dp_clk, dp_rst, A_ld, D_ld, D_st : in std_logic; ADDR_P : in
std_logic_vector (0 to 15); DIN : in std_logic_vector (0 to 7);
Write_match, Read_match : out std_logic; DOUT : out std_logic_vector
(0 to 7));
end datapath;
architecture SYN of datapath is
component comparator
port( addr_ld : in std_logic; addr_in : in std_logic_vector (0 to 15);
w_match, r_match : out std_logic);
end component;
component adder
port( num1, num2 : in std_logic_vector (0 to 7); sum : out
std_logic_vector (0 to 7));
end component;
component data_reg_0
port( clock, reset, load : in std_logic; data_in : in std_logic_vector
(0 to 7); data_out : out std_logic_vector (0 to 7));
end component;
component data_reg_1
port( clock, reset, load : in std_logic; data_in : in std_logic_vector
(0 to 7); data_out : out std_logic_vector (0 to 7));
end component;
signal reg2adder_5_port, reg2adder_1_port, adder2reg_4_port,
adder2reg_0_port, one_7_port, reg2adder_7_port, adder2reg_2_port,
reg2adder_3_port, adder2reg_6_port, one_0_port, reg2adder_2_port,
adder2reg_7_port, reg2adder_6_port, adder2reg_3_port, adder2reg_1_port,
reg2adder_4_port, reg2adder_0_port, adder2reg_5_port : std_logic;
begin
one_7_port <= '0';
one_0_port <= '1';
U1 : comparator port map( addr_ld => A_ld, addr_in(0) => ADDR_P(0),
addr_in(1) => ADDR_P(1), addr_in(2) => ADDR_P(2),
addr_in(3) => ADDR_P(3), addr_in(4) => ADDR_P(4),
addr_in(5) => ADDR_P(5), addr_in(6) => ADDR_P(6),
addr_in(7) => ADDR_P(7), addr_in(8) => ADDR_P(8),
addr_in(9) => ADDR_P(9), addr_in(10) => ADDR_P(10),
addr_in(11) => ADDR_P(11), addr_in(12) => ADDR_P(12)
, addr_in(13) => ADDR_P(13), addr_in(14) =>
ADDR_P(14), addr_in(15) => ADDR_P(15), w_match =>
Write_match, r_match => Read_match);
U2 : data_reg_1 port map( clock => dp_clk, reset => dp_rst, load => D_ld,
data_in(0) => DIN(0), data_in(1) => DIN(1),
data_in(2) => DIN(2), data_in(3) => DIN(3),
data_in(4) => DIN(4), data_in(5) => DIN(5),
data_in(6) => DIN(6), data_in(7) => DIN(7),
data_out(0) => reg2adder_7_port, data_out(1) =>
reg2adder_6_port, data_out(2) => reg2adder_5_port,
data_out(3) => reg2adder_4_port, data_out(4) =>
reg2adder_3_port, data_out(5) => reg2adder_2_port,
data_out(6) => reg2adder_1_port, data_out(7) =>
reg2adder_0_port);
U3 : adder port map( num1(0) => reg2adder_7_port, num1(1) =>
reg2adder_6_port, num1(2) => reg2adder_5_port,
num1(3) => reg2adder_4_port, num1(4) =>
reg2adder_3_port, num1(5) => reg2adder_2_port,
num1(6) => reg2adder_1_port, num1(7) =>
reg2adder_0_port, num2(0) => one_7_port, num2(1) =>
one_7_port, num2(2) => one_7_port, num2(3) =>
one_7_port, num2(4) => one_7_port, num2(5) =>
one_7_port, num2(6) => one_7_port, num2(7) =>
one_0_port, sum(0) => adder2reg_7_port, sum(1) =>
adder2reg_6_port, sum(2) => adder2reg_5_port, sum(3)
=> adder2reg_4_port, sum(4) => adder2reg_3_port,
sum(5) => adder2reg_2_port, sum(6) =>
adder2reg_1_port, sum(7) => adder2reg_0_port);
U4 : data_reg_0 port map( clock => dp_clk, reset => dp_rst, load => D_st,
data_in(0) => adder2reg_7_port, data_in(1) =>
adder2reg_6_port, data_in(2) => adder2reg_5_port,
data_in(3) => adder2reg_4_port, data_in(4) =>
adder2reg_3_port, data_in(5) => adder2reg_2_port,
data_in(6) => adder2reg_1_port, data_in(7) =>
adder2reg_0_port, data_out(0) => DOUT(0),
data_out(1) => DOUT(1), data_out(2) => DOUT(2),
data_out(3) => DOUT(3), data_out(4) => DOUT(4),
data_out(5) => DOUT(5), data_out(6) => DOUT(6),
data_out(7) => DOUT(7));
end SYN;
library IEEE,lsi_10k;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_textio.all;
use lsi_10k.COMPONENTS.all;
use work.CONV_PACK_ISA.all;
entity ISA is
port( CLK_P, RESET_P, IOR_P, IOW_P, ALE_P : in std_logic; ADDRESS_P : in
std_logic_vector (15 downto 0); DIN_P : in std_logic_vector (7 downto
0); DOUT_P : out std_logic_vector (7 downto 0));
end ISA;
architecture SYN of ISA is
component controller
port( ctrl_clk, ctrl_rst, IOR, IOW, ALE, WE_m, RE_m : in std_logic; Ald,
Dld, Dst : out std_logic);
end component;
component datapath
port( dp_clk, dp_rst, A_ld, D_ld, D_st : in std_logic; ADDR_P : in
std_logic_vector (0 to 15); DIN : in std_logic_vector (0 to 7);
Write_match, Read_match : out std_logic; DOUT : out
std_logic_vector (0 to 7));
end component;
signal WE_sig, Ald_sig, RE_sig, Dst_sig, Dld_sig : std_logic;
begin
U0 : controller port map( ctrl_clk => CLK_P, ctrl_rst => RESET_P, IOR =>
IOR_P, IOW => IOW_P, ALE => ALE_P, WE_m => WE_sig,
RE_m => RE_sig, Ald => Ald_sig, Dld => Dld_sig, Dst
=> Dst_sig);
U1 : datapath port map( dp_clk => CLK_P, dp_rst => RESET_P, A_ld => Ald_sig,
D_ld => Dld_sig, D_st => Dst_sig, ADDR_P(0) =>
ADDRESS_P(15), ADDR_P(1) => ADDRESS_P(14), ADDR_P(2)
=> ADDRESS_P(13), ADDR_P(3) => ADDRESS_P(12),
ADDR_P(4) => ADDRESS_P(11), ADDR_P(5) =>
ADDRESS_P(10), ADDR_P(6) => ADDRESS_P(9), ADDR_P(7)
=> ADDRESS_P(8), ADDR_P(8) => ADDRESS_P(7),
ADDR_P(9) => ADDRESS_P(6), ADDR_P(10) =>
ADDRESS_P(5), ADDR_P(11) => ADDRESS_P(4), ADDR_P(12)
=> ADDRESS_P(3), ADDR_P(13) => ADDRESS_P(2),
ADDR_P(14) => ADDRESS_P(1), ADDR_P(15) =>
ADDRESS_P(0), DIN(0) => DIN_P(7), DIN(1) => DIN_P(6)
, DIN(2) => DIN_P(5), DIN(3) => DIN_P(4), DIN(4) =>
DIN_P(3), DIN(5) => DIN_P(2), DIN(6) => DIN_P(1),
DIN(7) => DIN_P(0), Write_match => WE_sig,
Read_match => RE_sig, DOUT(0) => DOUT_P(7), DOUT(1)
=> DOUT_P(6), DOUT(2) => DOUT_P(5), DOUT(3) =>
DOUT_P(4), DOUT(4) => DOUT_P(3), DOUT(5) =>
DOUT_P(2), DOUT(6) => DOUT_P(1), DOUT(7) =>
DOUT_P(0));
end SYN;
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