----------------------------------------------------------------
-- UART Modeling Project: Transmitter Part
--
-- Test Bench #1 for UART Transmitter
-- by: Weijun Zhang, 05/2001
----------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.my_package.all;
----------------------------------------------------------------
entity test1_trans is
end test1_trans;
architecture bench1 of test1_trans is
component trans is
port( TRC: in std_logic;
MR: in std_logic;
TBRL: in std_logic;
SFD: in std_logic;
CRL: in std_logic;
CTRLWORD: in std_logic_vector(4 downto 0);
TBR: in std_logic_vector(7 downto 0);
TRE: out std_logic;
TBRE: out std_logic;
TRO: out std_logic
);
end component;
signal T_TRC,T_MR,T_TBRL,T_SFD,T_CRL: std_logic;
signal T_TRE,T_TBRE,T_TRO: std_logic;
signal T_TBR: std_logic_vector(7 downto 0);
signal T_CTRLWORD: std_logic_vector(4 downto 0);
begin
Unit: trans port map( T_TRC,T_MR,T_TBRL,T_SFD,T_CRL,
T_CTRLWORD,T_TBR,T_TRE,T_TBRE,T_TRO);
clk_sig: process
begin
T_TRC <='1';
wait for 5 ns;
T_TRC <= '0';
wait for 5 ns;
end process;
process
begin
T_MR <= '1'; -- initialization...
T_CRL <= '1';
T_CTRLWORD <= "11011";
T_SFD <= '0';
T_TBR <= "11000101";
T_TBRL <= '1';
wait for 50 ns;
T_CRL <= '0'; -- load ctrl word here
wait for 20 ns;
T_MR <= '0';
wait for 30 ns;
T_TBRL <= '0';
wait for 2800 ns;
T_SFD <= '1';
wait;
end process;
end bench1;
------------------------------------------------------------------
configuration CFG_TB of test1_trans is
for bench1
end for;
end CFG_TB;
------------------------------------------------------------------
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