library IEEE,lsi_10k;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_textio.all;
use lsi_10k.COMPONENTS.all;
package CONV_PACK_BRIDGE is
-- define attributes
attribute ENUM_ENCODING : STRING;
-- Declarations for conversion functions.
function std_logic_to_BIT(arg : in std_logic) return BIT;
function BIT_to_std_logic(arg : in BIT) return std_logic;
end CONV_PACK_BRIDGE;
package body CONV_PACK_BRIDGE is
-- std_logic to enum type function
function std_logic_to_BIT(arg : in std_logic) return BIT is
-- synopsys built_in SYN_FEED_THRU;
begin
case arg is
when '0' => return '0';
when '1' => return '1';
when others => assert FALSE -- this should not happen.
report "un-convertible value"
severity warning;
return '0';
end case;
end;
-- enum type to std_logic function
function BIT_to_std_logic(arg : in BIT) return std_logic is
-- synopsys built_in SYN_FEED_THRU;
begin
case arg is
when '0' => return '0';
when '1' => return '1';
when others => assert FALSE -- this should not happen.
report "un-convertible value"
severity warning;
return '0';
end case;
end;
end CONV_PACK_BRIDGE;
library IEEE,lsi_10k;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_textio.all;
use lsi_10k.COMPONENTS.all;
use work.CONV_PACK_BRIDGE.all;
entity BRIDGE is
port( clock, reset : in std_logic; rdy_in : in BIT; data_in : in
BIT_VECTOR (3 downto 0); rdy_out : out BIT; data_out : out
BIT_VECTOR (7 downto 0));
end BRIDGE;
architecture SYN of BRIDGE is
component AO3
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component AO7
port( A, B, C : in std_logic; Z : out std_logic);
end component;
component NR2
port( A, B : in std_logic; Z : out std_logic);
end component;
component AN3
port( A, B, C : in std_logic; Z : out std_logic);
end component;
component IV
port( A : in std_logic; Z : out std_logic);
end component;
component ND2
port( A, B : in std_logic; Z : out std_logic);
end component;
component ND3
port( A, B, C : in std_logic; Z : out std_logic);
end component;
component AO4
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component AO2
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component FD2P
port( D, CP, CD : in std_logic; Q, QN : out std_logic);
end component;
component IVA
port( A : in std_logic; Z : out std_logic);
end component;
component LD1P
port( D, G : in std_logic; Q, QN : out std_logic);
end component;
signal nextState_2_port, nextState_0_port, data_out_2_port, data_hi_3_port,
data_lo_2_port, data_out_6_port, currentState_2_port, rdy_in_port, n_401,
currentState_0_port, data_lo_0_port, data_out_4_port, data_hi_1_port,
data_out_0_port, data_in_1_port, nextState_1_port, data_in_3_port,
data_in_2_port, n_425, data_in_0_port, data_hi_0_port,
currentState_1_port, data_out_1_port, data_out_5_port, data_lo_1_port,
data_out_7_port, data_lo_3_port, data_out_3_port, rdy_out_port,
data_hi_2_port, n80, n81, n82, n83, n84, n85, n86, n87, n88, n89, n90,
n91, n92, n93, n94, n95, n96, n97, n98, n99, n100, n101, n102, n103, n104
, n105, n106, n107, n108, n109, n110, n111, n112, n113, n114 : std_logic;
begin
rdy_in_port <= BIT_to_std_logic(rdy_in);
data_in_3_port <= BIT_to_std_logic(data_in(3));
data_in_2_port <= BIT_to_std_logic(data_in(2));
data_in_1_port <= BIT_to_std_logic(data_in(1));
data_in_0_port <= BIT_to_std_logic(data_in(0));
rdy_out <= std_logic_to_BIT(rdy_out_port);
data_out(7) <= std_logic_to_BIT(data_out_7_port);
data_out(6) <= std_logic_to_BIT(data_out_6_port);
data_out(5) <= std_logic_to_BIT(data_out_5_port);
data_out(4) <= std_logic_to_BIT(data_out_4_port);
data_out(3) <= std_logic_to_BIT(data_out_3_port);
data_out(2) <= std_logic_to_BIT(data_out_2_port);
data_out(1) <= std_logic_to_BIT(data_out_1_port);
data_out(0) <= std_logic_to_BIT(data_out_0_port);
U39 : AO3 port map( A => currentState_0_port, B => n80, C => n81, D => n82,
Z => nextState_2_port);
U40 : AO7 port map( A => currentState_1_port, B => n83, C => n84, Z =>
nextState_1_port);
U41 : AO7 port map( A => currentState_0_port, B => n80, C => n85, Z =>
nextState_0_port);
U42 : NR2 port map( A => currentState_0_port, B => n82, Z => n_425);
U43 : AN3 port map( A => n82, B => n86, C => currentState_0_port, Z => n_401
);
U44 : IV port map( A => currentState_1_port, Z => n86);
U45 : IV port map( A => currentState_2_port, Z => n80);
U46 : ND2 port map( A => currentState_2_port, B => currentState_1_port, Z =>
n87);
U47 : ND2 port map( A => currentState_0_port, B => n80, Z => n83);
U48 : ND2 port map( A => currentState_2_port, B => n86, Z => n82);
U49 : ND2 port map( A => n89, B => n87, Z => n88);
U50 : NR2 port map( A => currentState_1_port, B => n91, Z => n90);
U51 : NR2 port map( A => currentState_2_port, B => n86, Z => n92);
U52 : NR2 port map( A => n87, B => currentState_0_port, Z => rdy_out_port);
U53 : IV port map( A => n83, Z => n91);
U54 : ND3 port map( A => n91, B => currentState_1_port, C => rdy_in_port, Z
=> n81);
U55 : AO4 port map( A => n86, B => currentState_0_port, C => n88, D => n94,
Z => n93);
U56 : AO2 port map( A => n92, B => n89, C => n90, D => rdy_in_port, Z => n85
);
U57 : IV port map( A => currentState_0_port, Z => n94);
U58 : IV port map( A => rdy_in_port, Z => n89);
U59 : IV port map( A => n93, Z => n84);
currentState_regx0x : FD2P port map( D => nextState_0_port, CP => clock, CD
=> n95, Q => currentState_0_port, QN => n96);
currentState_regx1x : FD2P port map( D => nextState_1_port, CP => clock, CD
=> n95, Q => currentState_1_port, QN => n97);
currentState_regx2x : FD2P port map( D => nextState_2_port, CP => clock, CD
=> n95, Q => currentState_2_port, QN => n98);
U60 : IVA port map( A => reset, Z => n95);
data_lo_regx3x : LD1P port map( D => data_in_3_port, G => n_401, Q =>
data_lo_3_port, QN => n99);
data_lo_regx2x : LD1P port map( D => data_in_2_port, G => n_401, Q =>
data_lo_2_port, QN => n100);
data_lo_regx1x : LD1P port map( D => data_in_1_port, G => n_401, Q =>
data_lo_1_port, QN => n101);
data_lo_regx0x : LD1P port map( D => data_in_0_port, G => n_401, Q =>
data_lo_0_port, QN => n102);
data_hi_regx3x : LD1P port map( D => data_in_3_port, G => n_425, Q =>
data_hi_3_port, QN => n103);
data_hi_regx2x : LD1P port map( D => data_in_2_port, G => n_425, Q =>
data_hi_2_port, QN => n104);
data_hi_regx1x : LD1P port map( D => data_in_1_port, G => n_425, Q =>
data_hi_1_port, QN => n105);
data_hi_regx0x : LD1P port map( D => data_in_0_port, G => n_425, Q =>
data_hi_0_port, QN => n106);
data_out_regx7x : LD1P port map( D => data_lo_3_port, G => rdy_out_port, Q
=> data_out_7_port, QN => n107);
data_out_regx6x : LD1P port map( D => data_lo_2_port, G => rdy_out_port, Q
=> data_out_6_port, QN => n108);
data_out_regx5x : LD1P port map( D => data_lo_1_port, G => rdy_out_port, Q
=> data_out_5_port, QN => n109);
data_out_regx4x : LD1P port map( D => data_lo_0_port, G => rdy_out_port, Q
=> data_out_4_port, QN => n110);
data_out_regx3x : LD1P port map( D => data_hi_3_port, G => rdy_out_port, Q
=> data_out_3_port, QN => n111);
data_out_regx2x : LD1P port map( D => data_hi_2_port, G => rdy_out_port, Q
=> data_out_2_port, QN => n112);
data_out_regx1x : LD1P port map( D => data_hi_1_port, G => rdy_out_port, Q
=> data_out_1_port, QN => n113);
data_out_regx0x : LD1P port map( D => data_hi_0_port, G => rdy_out_port, Q
=> data_out_0_port, QN => n114);
end SYN;
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