library IEEE,lsi_10k;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_textio.all;
use lsi_10k.COMPONENTS.all;
package CONV_PACK_gcd is
-- define attributes
attribute ENUM_ENCODING : STRING;
-- define any necessary types
-- type UNSIGNED is array (INTEGER range <>) of std_logic;
end CONV_PACK_gcd;
library IEEE,lsi_10k;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_textio.all;
use lsi_10k.COMPONENTS.all;
use work.CONV_PACK_gcd.all;
entity gcd is
port( clk, rst, go_i : in std_logic; x_i, y_i : in UNSIGNED (3 downto 0);
d_o : out UNSIGNED (3 downto 0));
end gcd;
architecture SYN of gcd is
component NR2
port( A, B : in std_logic; Z : out std_logic);
end component;
component AO7
port( A, B, C : in std_logic; Z : out std_logic);
end component;
component ND2
port( A, B : in std_logic; Z : out std_logic);
end component;
component AN2
port( A, B : in std_logic; Z : out std_logic);
end component;
component AO5
port( A, B, C : in std_logic; Z : out std_logic);
end component;
component IV
port( A : in std_logic; Z : out std_logic);
end component;
component AO4
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component ND3
port( A, B, C : in std_logic; Z : out std_logic);
end component;
component EON1
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component AO2
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component EO
port( A, B : in std_logic; Z : out std_logic);
end component;
component EN
port( A, B : in std_logic; Z : out std_logic);
end component;
component AO6
port( A, B, C : in std_logic; Z : out std_logic);
end component;
component ND4
port( A, B, C, D : in std_logic; Z : out std_logic);
end component;
component BTS4P
port( A, E : in std_logic; Z : out std_logic);
end component;
component FJK2SP
port( J, K, CP, CD, TI, TE : in std_logic; Q, QN : out std_logic);
end component;
component FD2P
port( D, CP, CD : in std_logic; Q, QN : out std_logic);
end component;
component IVA
port( A : in std_logic; Z : out std_logic);
end component;
component FDS2LP
port( D, CP, CR, LD : in std_logic; Q, QN : out std_logic);
end component;
signal State_1_port, State_0_port, d_o_Q123x2x, Data_X143x0x, State93x0x,
Data_Yx2x, Data_Yx0x, Data_X_0_port, Data_X143x2x, d_o_Q123x0x,
Data_Y149x0x, n197x0x, n153x0x, Data_Y149x2x, Data_X_2_port,
Data_X_3_port, Data_Y149x3x, Data_X_1_port, Data_Y149x1x, d_o_Q123x1x,
Data_X143x3x, n147x0x, Data_Yx1x, Data_Yx3x, Data_X143x1x, d_o_Q123x3x,
State93x1x, n397, n398, n399, n400, n401, n402, n403, n404, n405, n406,
n407, n408, n409, n410, n411, n412, n413, n414, n415, n416, n417, n418,
n419, n420, n421, n422, n423, n424, n425, n426, n427, n428, n429, n430,
n431, n432, n433, n434, n435, n436, n437, n438, n439, n440, n441, n442,
n443, n444, n445, n446, n447, n448, n449, n450, n451, n452, n453, n454,
n455, n456, n457, n458, n459, n460, n461, n462, n463, n464, n465, n466,
n467, n468, n469, n470, n471, n472, n473, n474, n475, n476, n477, n478,
n479, n480, n481, n482, n483, n484, n485, n486 : std_logic;
begin
U117 : NR2 port map( A => State_1_port, B => n397, Z => State93x1x);
U118 : AO7 port map( A => n460, B => n398, C => n399, Z => Data_X143x3x);
U119 : AO7 port map( A => n460, B => n400, C => n401, Z => Data_X143x2x);
U120 : AO7 port map( A => n460, B => n402, C => n403, Z => Data_X143x1x);
U121 : ND2 port map( A => n404, B => n405, Z => Data_X143x0x);
U122 : AO7 port map( A => n406, B => n407, C => n408, Z => n147x0x);
U123 : AO7 port map( A => n460, B => n409, C => n410, Z => Data_Y149x3x);
U124 : AO7 port map( A => n460, B => n411, C => n412, Z => Data_Y149x2x);
U125 : AO7 port map( A => n460, B => n413, C => n414, Z => Data_Y149x1x);
U126 : ND2 port map( A => n415, B => n416, Z => Data_Y149x0x);
U127 : AO7 port map( A => n417, B => n406, C => n408, Z => n153x0x);
U128 : ND2 port map( A => n406, B => n418, Z => State93x0x);
U129 : NR2 port map( A => n420, B => Data_Yx1x, Z => n419);
U130 : AN2 port map( A => n422, B => Data_Yx2x, Z => n421);
U131 : ND2 port map( A => n424, B => n409, Z => n423);
U132 : ND2 port map( A => n426, B => Data_Yx1x, Z => n425);
U133 : AO5 port map( A => n428, B => n400, C => Data_Yx2x, Z => n427);
U134 : IV port map( A => Data_Yx0x, Z => n429);
U135 : IV port map( A => Data_X_3_port, Z => n398);
U136 : IV port map( A => Data_Yx3x, Z => n409);
U137 : IV port map( A => Data_X_1_port, Z => n402);
U138 : IV port map( A => Data_Yx1x, Z => n413);
U139 : IV port map( A => Data_X_2_port, Z => n400);
U140 : IV port map( A => Data_Yx2x, Z => n411);
U141 : IV port map( A => State_1_port, Z => n430);
U142 : IV port map( A => n460, Z => n431);
U143 : NR2 port map( A => n429, B => Data_X_0_port, Z => n420);
U144 : AO4 port map( A => n413, B => n432, C => Data_X_1_port, D => n419, Z
=> n422);
U145 : AO4 port map( A => Data_Yx2x, B => n422, C => n421, D => n400, Z =>
n424);
U146 : ND3 port map( A => n433, B => n397, C => State_1_port, Z => n406);
U147 : AN2 port map( A => n460, B => n418, Z => n408);
U148 : EON1 port map( A => n409, B => n424, C => n398, D => n423, Z => n407)
;
U149 : IV port map( A => State_0_port, Z => n397);
U150 : ND2 port map( A => Data_X_0_port, B => n429, Z => n426);
U151 : AO2 port map( A => n413, B => n434, C => n425, D => Data_X_1_port, Z
=> n428);
U152 : NR2 port map( A => n431, B => n430, Z => n435);
U153 : NR2 port map( A => n431, B => State_1_port, Z => n436);
U154 : EO port map( A => n427, B => n438, Z => n437);
U155 : AO2 port map( A => n440, B => n434, C => n441, D => n426, Z => n439);
U156 : EN port map( A => n438, B => n424, Z => n442);
U157 : AO2 port map( A => n440, B => n420, C => n441, D => n432, Z => n443);
U158 : NR2 port map( A => n440, B => n438, Z => n444);
U159 : AO2 port map( A => n435, B => n437, C => y_i(3), D => n436, Z => n410
);
U160 : AO2 port map( A => n445, B => n435, C => y_i(2), D => n436, Z => n412
);
U161 : AO2 port map( A => n435, B => n439, C => y_i(1), D => n436, Z => n414
);
U162 : AO2 port map( A => y_i(0), B => n436, C => n435, D => n434, Z => n416
);
U163 : AO2 port map( A => Data_Yx0x, B => n431, C => n420, D => State_1_port
, Z => n415);
U164 : AO2 port map( A => n435, B => n442, C => x_i(3), D => n436, Z => n399
);
U165 : AO2 port map( A => n446, B => n435, C => x_i(2), D => n436, Z => n401
);
U166 : AO2 port map( A => n435, B => n443, C => x_i(1), D => n436, Z => n403
);
U167 : AO2 port map( A => x_i(0), B => n436, C => n435, D => n420, Z => n405
);
U168 : AO2 port map( A => Data_X_0_port, B => n431, C => n434, D =>
State_1_port, Z => n404);
U169 : AO6 port map( A => n397, B => n433, C => n430, Z => n197x0x);
U170 : ND3 port map( A => n397, B => n430, C => go_i, Z => n418);
U171 : IV port map( A => n426, Z => n434);
U172 : IV port map( A => n420, Z => n432);
U173 : ND4 port map( A => n432, B => n426, C => n447, D => n444, Z => n433);
U174 : IV port map( A => n407, Z => n417);
U175 : AO2 port map( A => n411, B => Data_X_2_port, C => Data_Yx2x, D =>
n400, Z => n447);
U176 : AO4 port map( A => Data_Yx1x, B => Data_X_1_port, C => n413, D =>
n402, Z => n441);
U177 : AO2 port map( A => Data_Yx3x, B => Data_X_3_port, C => n409, D =>
n398, Z => n438);
U178 : EO port map( A => n428, B => n447, Z => n445);
U179 : EN port map( A => n422, B => n447, Z => n446);
U180 : IV port map( A => n441, Z => n440);
d_o_trix2x : BTS4P port map( A => d_o_Q123x2x, E => n448, Z => d_o(2));
d_o_trix0x : BTS4P port map( A => d_o_Q123x0x, E => n449, Z => d_o(0));
d_o_trix1x : BTS4P port map( A => d_o_Q123x1x, E => n450, Z => d_o(1));
d_o_trix3x : BTS4P port map( A => d_o_Q123x3x, E => n451, Z => d_o(3));
d_o_regx3x : FJK2SP port map( J => n452, K => n452, CP => clk, CD => n460,
TI => Data_X_3_port, TE => n197x0x, Q => d_o_Q123x3x
, QN => n469);
n452 <= '0';
d_o_regx2x : FJK2SP port map( J => n453, K => n453, CP => clk, CD => n460,
TI => Data_X_2_port, TE => n197x0x, Q => d_o_Q123x2x
, QN => n470);
n453 <= '0';
d_o_regx1x : FJK2SP port map( J => n454, K => n454, CP => clk, CD => n460,
TI => Data_X_1_port, TE => n197x0x, Q => d_o_Q123x1x
, QN => n471);
n454 <= '0';
d_o_regx0x : FJK2SP port map( J => n455, K => n455, CP => clk, CD => n460,
TI => Data_X_0_port, TE => n197x0x, Q => d_o_Q123x0x
, QN => n472);
n455 <= '0';
d_o_tri_enable_regx3x : FJK2SP port map( J => n456, K => n456, CP => clk, CD
=> n460, TI => State_0_port, TE => n197x0x, Q =>
n473, QN => n451);
n456 <= '0';
d_o_tri_enable_regx2x : FJK2SP port map( J => n457, K => n457, CP => clk, CD
=> n460, TI => State_0_port, TE => n197x0x, Q =>
n474, QN => n448);
n457 <= '0';
d_o_tri_enable_regx1x : FJK2SP port map( J => n458, K => n458, CP => clk, CD
=> n460, TI => State_0_port, TE => n197x0x, Q =>
n475, QN => n450);
n458 <= '0';
d_o_tri_enable_regx0x : FJK2SP port map( J => n459, K => n459, CP => clk, CD
=> n460, TI => State_0_port, TE => n197x0x, Q =>
n476, QN => n449);
n459 <= '0';
State_regx0x : FD2P port map( D => State93x0x, CP => clk, CD => n460, Q =>
State_0_port, QN => n477);
State_regx1x : FD2P port map( D => State93x1x, CP => clk, CD => n460, Q =>
State_1_port, QN => n478);
U189 : IVA port map( A => rst, Z => n460);
Data_X_regx3x : FDS2LP port map( D => Data_X143x3x, CP => clk, CR => n461,
LD => n147x0x, Q => Data_X_3_port, QN => n479);
n461 <= '1';
Data_X_regx2x : FDS2LP port map( D => Data_X143x2x, CP => clk, CR => n462,
LD => n147x0x, Q => Data_X_2_port, QN => n480);
n462 <= '1';
Data_X_regx1x : FDS2LP port map( D => Data_X143x1x, CP => clk, CR => n463,
LD => n147x0x, Q => Data_X_1_port, QN => n481);
n463 <= '1';
Data_X_regx0x : FDS2LP port map( D => Data_X143x0x, CP => clk, CR => n464,
LD => n147x0x, Q => Data_X_0_port, QN => n482);
n464 <= '1';
Data_Y_regx3x : FDS2LP port map( D => Data_Y149x3x, CP => clk, CR => n465,
LD => n153x0x, Q => Data_Yx3x, QN => n483);
n465 <= '1';
Data_Y_regx2x : FDS2LP port map( D => Data_Y149x2x, CP => clk, CR => n466,
LD => n153x0x, Q => Data_Yx2x, QN => n484);
n466 <= '1';
Data_Y_regx1x : FDS2LP port map( D => Data_Y149x1x, CP => clk, CR => n467,
LD => n153x0x, Q => Data_Yx1x, QN => n485);
n467 <= '1';
Data_Y_regx0x : FDS2LP port map( D => Data_Y149x0x, CP => clk, CR => n468,
LD => n153x0x, Q => Data_Yx0x, QN => n486);
n468 <= '1';
end SYN;
<div align="center"><br /><script type="text/javascript"><!--
google_ad_client = "pub-7293844627074885";
//468x60, Created at 07. 11. 25
google_ad_slot = "8619794253";
google_ad_width = 468;
google_ad_height = 60;
//--></script>
<script type="text/javascript" src="http://pagead2.googlesyndication.com/pagead/show_ads.js">
</script><br /> </div>