-- --multiplexer design --control signal is juht_sig --it is chosen from 2 signals with length 8 bits --if control signal is 1 then input A_IN is chosen --if 0 then input B_IN is chosen to the output OUT_SIG library IEEE; use IEEE.std_logic_1164.all; entity MUX is port (A_IN : in std_logic_vector(7 downto 0); B_IN : in std_logic_vector(7 downto 0); JUHT_SIG : in std_logic; OUT_SIG : out std_logic_vector(3 downto 0)); end MUX; architecture RTL of MUX is begin DISP_MUX: process (A_IN, B_IN) begin if JUHT_SIG = '1' then OUT_SIG <= A_IN; else OUT_SIG <= B_IN; end if; end DISP_MUX; end RTL; <div align="center"><br /><script type="text/javascript"><!-- google_ad_client = "pub-7293844627074885"; //468x60, Created at 07. 11. 25 google_ad_slot = "8619794253"; google_ad_width = 468; google_ad_height = 60; //--></script> <script type="text/javascript" src="http://pagead2.googlesyndication.com/pagead/show_ads.js"> </script><br /> </div>