backTTL을이용한 16비트 카운터를 PLD로 할 수는 없을까요?
>#1545 인지혜 (XmasKid )
>[질문]16bit counter + latch=? 01/22 15:15 8 line
>
>16bit counter(74ls191*4개) 와 latch(74ls373*2개)를
>하나의 PLD로 구울 수 있을까 요?
>그렇게 되면 복잡 한 보드 가 훨씬 쉽게 될거 같은데...
>
PLD로 만드는 이유중의 하나가 바로 이와 같이 회로의 집적화 이지요
>PLD굽는건 FPGA(MACH같은것)과 비슷하게...
>programmer를 구입해야 하는건가요?
>
>그럼....답.변 부탁드 립니다...
ISP Device를 쓰면 Down Load Cable응 이용해서 간단하게 PLD를 제작할수 있습니다. 질문하신 내용을 VHDL로 간단하게 만들어 보면...
-------------------------------------------------------
-- 16-Bits Synchronous Up/Down counter /w Load Control
-- and Output Latch
--
-- goodkook@csvlsi.kyunghee.ac.kr
-- http://163.180.122.171
-- Kyunghee Univ., EE, CSA & VLSI Design Lab.
------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity count16 is
port ( count_in : in std_logic_vector(15 downto 0);
load : in std_logic;
up_cnt : in std_logic;
oe : in std_logic;
le : in std_logic;
clk : in std_logic;
count_out : out std_logic_vector(15 downto 0));
end count16;
architecture behave of count16 is
signal s_cnt16, s_count_out : std_logic_vector(15 downto 0);
begin
-- 16-Bits Synchronous Up/Down counter /w Load Control
u_cnt : process(clk, load, count_in, up_cnt)
variable v_cnt16 : unsigned(15 downto 0);
begin
if (clk'event and clk='1') then
if (load='1') then
v_cnt16 := unsigned(count_in);
else
if (up_cnt='1') then
v_cnt16 := v_cnt16 + "1";
else
v_cnt16 := v_cnt16 - "1";
end if;
end if;
end if;
s_cnt16 <= std_logic_vector(v_cnt16);
end process;
-- Level Sensitive Output Latch
latch : process(le, s_cnt16)
begin
if (le='0') then
s_count_out <= s_cnt16;
end if;
end process;
count_out <= (others=> 'Z') when oe='1' else
s_count_out;
end behave;
|
PeakVHDL/FPGA툴로 Vantis(MACH)를 선택해서 합성하였더니....
tri-states = 16
flip flops with no set or reset = 16
latches with no set or reset = 16
combinational logic area estimate = 126 two input gates
이라고 나왔네요. 상당히 정확하죠? 합성후 리포트 화일 (metammor.log)은 다음과 같습니다.
-- 16-Bits Synchronous Up/Down counter /w Load Control METAMOR VHDL Logic Compiler 3.0.6 (01/08/98) Copyright (c) 1992-98 Metamor, Inc. All Rights Reserved Compiling for: Vantis analyze.... 1 sec elaborate design "count16" process : u_cnt 2 sec Inferred structure : flip flop: s_cnt16 15 COUNT16.VHD line 31 flip flop: s_cnt16 14 COUNT16.VHD line 31 flip flop: s_cnt16 13 COUNT16.VHD line 31 flip flop: s_cnt16 12 COUNT16.VHD line 31 flip flop: s_cnt16 11 COUNT16.VHD line 31 flip flop: s_cnt16 10 COUNT16.VHD line 31 flip flop: s_cnt16 9 COUNT16.VHD line 31 flip flop: s_cnt16 8 COUNT16.VHD line 31 flip flop: s_cnt16 7 COUNT16.VHD line 31 flip flop: s_cnt16 6 COUNT16.VHD line 31 flip flop: s_cnt16 5 COUNT16.VHD line 31 flip flop: s_cnt16 4 COUNT16.VHD line 31 flip flop: s_cnt16 3 COUNT16.VHD line 31 flip flop: s_cnt16 2 COUNT16.VHD line 31 flip flop: s_cnt16 1 COUNT16.VHD line 31 flip flop: s_cnt16 0 COUNT16.VHD line 31 process : latch 0 sec Inferred structure : latch: s_count_out 0 COUNT16.VHD line 49 latch: s_count_out 1 COUNT16.VHD line 49 latch: s_count_out 2 COUNT16.VHD line 49 latch: s_count_out 3 COUNT16.VHD line 49 latch: s_count_out 4 COUNT16.VHD line 49 latch: s_count_out 5 COUNT16.VHD line 49 latch: s_count_out 6 COUNT16.VHD line 49 latch: s_count_out 7 COUNT16.VHD line 49 latch: s_count_out 8 COUNT16.VHD line 49 latch: s_count_out 9 COUNT16.VHD line 49 latch: s_count_out 10 COUNT16.VHD line 49 latch: s_count_out 11 COUNT16.VHD line 49 latch: s_count_out 12 COUNT16.VHD line 49 latch: s_count_out 13 COUNT16.VHD line 49 latch: s_count_out 14 COUNT16.VHD line 49 latch: s_count_out 15 COUNT16.VHD line 49 assign : 0 sec Inferred structure : tristate: count_out 0 COUNT16.VHD line 54 tristate: count_out 1 COUNT16.VHD line 54 tristate: count_out 2 COUNT16.VHD line 54 tristate: count_out 3 COUNT16.VHD line 54 tristate: count_out 4 COUNT16.VHD line 54 tristate: count_out 5 COUNT16.VHD line 54 tristate: count_out 6 COUNT16.VHD line 54 tristate: count_out 7 COUNT16.VHD line 54 tristate: count_out 8 COUNT16.VHD line 54 tristate: count_out 9 COUNT16.VHD line 54 tristate: count_out 10 COUNT16.VHD line 54 tristate: count_out 11 COUNT16.VHD line 54 tristate: count_out 12 COUNT16.VHD line 54 tristate: count_out 13 COUNT16.VHD line 54 tristate: count_out 14 COUNT16.VHD line 54 tristate: count_out 15 COUNT16.VHD line 54 elaborate "count16" 2 sec optimize "count16".... 4 sec tri-states = 16 flip flops with no set or reset = 16 latches with no set or reset = 16 combinational logic area estimate = 126 two input gates format.... 0 sec no errors. compile time = 7 sec peak dynamic memory allocation = 5.434 Mbyte. |
mailto:goodkook
CSA & VLSI Design Lab. Kyunghee Univ